D685A1156U01流量计模块,ABB中文PDF使用手册

ROM周期时间可编程为4到11个总线时钟周期。数据传输为32位宽。参考单板计算机程序员参考指南。SCSI传输MVME177包括一个SCSI大容量存储总线接口，具有DMA控制器。SCSI DMA控制器使用FIFO缓冲区来将8位SCSI总线连接到32位本地总线。FIFO缓冲区允许SCSI DMA控制器有效地将数据传输到本地总线在四个长单词突发。这减少了本地总线使用量SCSI设备。

D685A1156U01流量计模块突发的第一次长字传输，禁止监听，要求：❏ 奇偶校验关闭的四个总线时钟，以及❏ 奇偶校验开启的五个总线时钟其余三次传输中的每一次都需要一个总线时钟。DMA控制器在25 MHz时的传输速率为44MB/s奇偶校验关闭。假设上的连续传输速率为5MB/sSCSI总线的传输使用了本地总线带宽的12%从SCSI总线。LAN DMA传输MVME177包括与DMA控制器的LAN接口。这个LAN DMA控制器使用FIFO缓冲区连接串行LAN总线到32位本地总线。FIFO缓冲区允许LAN DMA控制器有效地将数据传输到本地总线。82596CA不执行MC68060兼容的突发周期，因此，LAN DMA控制器不使用突发传输。DRAM写入周期需要3个时钟周期，读取周期需要：❏ 奇偶校验关闭和❏ 奇偶校验开启时的6个时钟周期LAN DMA控制器的传输速率在25时为20MB/sMHz（或30 MHz时为24MB/s），奇偶校验关闭。假设LAN总线上的连续传输速率为1MB/s，为局域网总线的传输使用本地总线带宽。远程状态和控制远程状态和控制连接器J3是一个20针连接器位于MVME177前面板后面。它提供了系统设计师可以灵活访问关键指标并重置功能。这允许系统设计师构建重置/中止/LED面板，可从MVME177。除了LED和复位和中止开关访问，该连接器还包括：❏ 两个通用TTL级输入/输出引脚❏ 一个通用中断引脚，也可以作为

触发器输入。该中断引脚为电平可编程The ROM cycle time is programmable from 4 to 11 bus clock cycles.

The data transfers are 32 bits wide. Refer to the Single Board

Computers Programmer's Reference Guide.

SCSI Transfers

The MVME177 includes a SCSI mass storage bus interface with

DMA controller. The SCSI DMA controller uses a FIFO buffer to

interface the 8-bit SCSI bus to the 32-bit local bus. The FIFO buffer

allows the SCSI DMA controller to efficiently transfer data to the

local bus in four longword bursts. This reduces local bus usage by

the SCSI device.

The first longword transfer of a burst, with snooping disabled,

requires:

❏ Four bus clocks with parity off, and

❏ Five bus clocks with parity on

Each of the remaining three transfers requires one bus clock.

The transfer rate of the DMA controller is 44MB/sec at 25 MHz

with parity off. Assuming a continuous transfer rate of 5MB/sec on

the SCSI bus, 12% of the local bus bandwidth is used by transfers

from the SCSI bus. LAN DMA Transfers

The MVME177 includes a LAN interface with DMA controller. The

LAN DMA controller uses a FIFO buffer to interface the serial LAN

bus to the 32-bit local bus. The FIFO buffer allows the LAN DMA

controller to efficiently transfer data to the local bus.

The 82596CA does not execute MC68060 compatible burst cycles,

therefore the LAN DMA controller does not use burst transfers.

DRAM write cycles require 3 clock cycles, and read cycles require:

❏ 5 clock cycles with parity off and

❏ 6 clock cycles with parity on

The transfer rate of the LAN DMA controller is 20MB/sec at 25

MHz (or 24MB/sec at 30 MHz) with parity off. Assuming a

continuous transfer rate of 1MB/sec on the LAN bus, 5% (or 4%) of

the local bus bandwidth is used by transfers from the LAN bus.

Remote Status and Control

The remote status and control connector, J3, is a 20-pin connector

located behind the front panel of the MVME177. It provides system

designers the flexibility to access critical indicator and reset

functions. This allows a system designer to construct a

RESET/ABORT/LED panel that can be located remotely from the

MVME177.

In addition to the LED and the RESET and ABORT switches access,

this connector also includes:

❏ Two general purpose TTL-level I/O pins

❏ One general purpose interrupt pin which can also function as

a trigger input. This interrupt pin is level programmable