D674A906U01流量计,ABB中文PDF说明书在线阅读

VMEchip2中提供了看门狗定时器功能。当看门狗定时器已启用，必须在编程时间或超时。看门狗定时器可以编程生成：❏ 系统复位信号❏ 本地重置信号，或❏ 超时时的板故障信号参考单板机程序员手册中的VMEchip2有关详细编程信息的参考指南。软件可编程硬件中断提供了八个软件可编程硬件中断通过VMEchip2。这些中断允许软件创建硬件中断。

D674A906U01流量计,参考单板中的VMEchip2计算机程序员详细编程参考指南信息MVME177为本地总线提供超时功能。什么时候计时器启用，本地总线访问超时，传输错误确认（TEA）信号被发送到本地总线主机。这个超时值可由软件选择：本地总线计时器在VMEbus绑定周期内不工作。VMEbus绑定周期由VMEbus访问计时器计时，并且VMEbus全局计时器。参考单板中的VMEchip2计算机程序员详细编程参考指南信息模块标识软件区分MVME177模块和MVME176模块使用输入/输出控制寄存器（GPI）位3。在…上对于MVME177，输入/输出控制寄存器（GPI）位3为输出（打开）“高”（一）。在MVME176上，输入/输出控制寄存器（GPI）位3为“低”（零）硬接线（短路）。定时性能

本节提供了MVME177。各种MVME177的设计工作频率为50 MHz或60 MHz（当060支持时）。本地总线到DRAM循环时间PCCHIP2和VMEchip2具有相同的本地总线接口与MC68060一样定时，因此以下循环时间适用于PCCHIP2和VMEchip2。对板上DRAM的读取访问需要5个总线时钟周期，总线错误在当前周期中报告。对板载DRAM的写入访问需要2个总线时钟周期。突发读取访问需要8（5-1-1-1）个总线时钟周期当前周期中报告的错误。突发写入周期需要5（2-1-1-1）总线时钟周期。

A watchdog timer function is provided in the VMEchip2. When the

watchdog timer is enabled, it must be reset by software within the

programmed time or it times out. The watchdog timer can be

programmed to generate:

❏ A SYSRESET signal

❏ Local reset signal, or

❏ Board fail signal if it times out

Refer to the VMEchip2 in the Single Board Computers Programmer's

Reference Guide for detailed programming information.

Software-Programmable Hardware Interrupts

Eight software-programmable hardware interrupts are provided

by the VMEchip2. These interrupts allow software to create a

hardware interrupt. Refer to the VMEchip2 in the Single Board

Computers Programmer's Reference Guide for detailed programming

information. The MVME177 provides a time-out function for the local bus. When

the timer is enabled and a local bus access times out, a Transfer

Error Acknowledge (TEA) signal is sent to the local bus master. The

time-out value is selectable by software for:The local bus timer does not operate during VMEbus bound cycles.

VMEbus bound cycles are timed by the VMEbus access timer and

the VMEbus global timer. Refer to the VMEchip2 in the Single Board

Computers Programmer's Reference Guide for detailed programming

information. Module Identification

Software distinguishes between an MVME177 module and an

MVME176 module by use of the I/O control register (GPI) bit 3. On

an MVME177, the I/O control register (GPI) bit 3 is out (open) for a

“high” (one). On an MVME176, the I/O control register (GPI) bit 3

is hardwired in (shorted) for a “low” (zero).

Timing Performance

This section provides the performance information for the

MVME177. Various MVME177s are designed to operate at 50 MHz

or 60 MHz (when supported by 060).

Local Bus to DRAM Cycle Times

The PCCchip2 and VMEchip2 have the same local bus interface

timing as the MC68060, therefore the following cycle times also

apply to the PCCchip2 and the VMEchip2. Read accesses toonboard DRAM require 5 bus clock cycles with the bus error

reported in the current cycle. Write accesses to onboard DRAM

require 2 bus clock cycles.

Burst read accesses require 8 (5-1-1-1) bus clock cycles with the bus

error reported in the current cycle. Burst write cycles require 5

(2-1-1-1) bus clock cycles.