BENTLY 330901-05-32-05-02-00电缆存储电路板时，如果有电池，则应断开以延长电池寿命。这在以下方面尤为重要：环境温度高。MVME177板，带备用电池装运时电池已断开。电池的电源线暴露在因此，电路板不应放置在导电板上表面或储存在导电袋中，除非拆下电池。注：锂电池包含易燃材料例如锂和有机溶剂。如果电池受到虐待或处理不当可能爆裂并点燃，可能导致受伤和/或火灾。
BENTLY 330901-05-32-05-02-00电缆在处理锂电池时，仔细遵循以下列出的预防措施，以便防止事故：要从模块中卸下电池，请小心拉动电池从插座。车载DRAMMVME177板载DRAM位于夹层板上。夹层板使用错误检查和纠正（ECC）用于纠正单位错误和检测双位错误的保护。当出现位错误时，可以启用中断或总线异常检测。内存夹层的中断输出为连接到VMEchip2 PEIRQ*中断输入。可以堆叠两块夹层板，以提供256MB的机载RAM。主板和单个夹层板一起吃一个槽。堆叠配置需要两VME板槽。DRAM是四路交错的，以高效地支持缓存突发周期。DRAM地图解码器可以编程以适应不同的基址和夹层板的大小。这个车载DRAM由本地总线重置禁用，必须在可以访问DRAM之前编程。请参阅单板计算机程序员参考指南中的MCECC有关详细的编程信息。大多数DRAM设备在DRAM完全运行之前，需要一些访问周期操作的通常情况下，车载设备满足此要求刷新电路和正常DRAM初始化。然而软件应确保至少10个初始化周期对每个RAM组执行。
When a board is stored, if the battery is present, it should be
disconnected to prolong battery life. This is especially important at
high ambient temperatures. MVME177 boards with battery backup
are shipped with the batteries disconnected.
The power leads from the battery are exposed on the solder side of
the board, therefore the board should not be placed on a conductive
surface or stored in a conductive bag unless the battery is removed.
Note Lithium batteries incorporate inflammable materials
such as lithium and organic solvents. If lithium
batteries are mistreated or handled incorrectly, they
may burst open and ignite, possibly resulting in injury
and/or fire. When dealing with lithium batteries,
carefully follow the precautions listed below in order to
prevent accidents:To remove the battery from the module, carefully pull the battery
from the socket.
Onboard DRAM
The MVME177 onboard DRAM is located on a mezzanine board.
The mezzanine boards use error checking and correction (ECC)
protection to correct single-bit errors and detect double-bit errors.
Interrupts or bus exception can be enabled when a bit error is
detected. The interrupt output from the memory mezzanine is
connected to the VMEchip2 PEIRQ* interrupt input.Two mezzanine boards may be stacked to provide 256MB of
onboard RAM. The main board and a single mezzanine board
together take one slot. The stacked configuration requires two
VMEboard slots. The DRAM is four-way interleaved to efficiently
support cache burst cycles.
The DRAM map decoder can be programmed to accommodate
different base address(es) and sizes of mezzanine boards. The
onboard DRAM is disabled by a local bus reset and must be
programmed before the DRAM can be accessed. Refer to the
MCECC in the Single Board Computers Programmer's Reference Guide
for detailed programming information. Most DRAM devices
require some number of access cycles before the DRAMs are fully
operational. Normally this requirement is met by the onboard
refresh circuitry and normal DRAM initialization. However,
software should insure a minimum of 10 initialization cycles are
performed to each bank of RAM.
