EMERSON KJ2002X1-CA1 CPU模块
VME控制下表显示了VMIVME-7750（从BAR0偏移）的寄存器定义。EC_SEL 0主大端点启用位1=大端点0=小端点位SEC_SEL 1从大端点激活位1=大端点0＝小端点ABLE 2辅助BERR逻辑启用位1＝Aux。BERR启用0=辅助。BERR禁用BTO 3总线错误计时器启用1=启用0=禁用BTOV[1:0]5:4超时值00-16uS 01-64uS 10-256uS 11-1.00mS BERRI 6 BERR中断启用1=中断启用0=中断禁用BERRST 7 BERR状态读取/清除位1=清除BERR状态0=不执行任何操作SFENA 8在WDT超时时启用VME SYSFAIL生成0=禁用未使用9未使用BPENA10 Endian转换旁路位1=旁路0=未绕过ECENA 11 Endian转换位1=启用0=禁用未使用31:12未使用VBAR 0x04 VME_ADDR所有锁存VME地址VBAM 0x08 VME_ADDR5:0锁存VMM地址修改器未使用31:6未使用
VME Control
The following table shows the register definitions for the VMIVME-7750 (offset from
BAR0).EC_SEL 0 Master big-endian enable bit 1=Big Endian
0=Little Endian bit
SEC_SEL 1 Slave Big-Endian enable bit 1=Big Endian
0=Little Endian
ABLE 2 Auxiliary BERR logic enable bit
1=Aux. BERR enabled 0=Aux. BERR disabled
BTO 3 Bus error timer enabled 1=enabled 0=disabled
BTOV [1:0] 5:4 Timeout value
00 - 16uS
01 - 64uS
10 -256uS
11 - 1.00mS
BERRI 6 BERR interrupt enable 1=Interrupt enabled
0=Interrupt disabled
BERRST 7 BERR status read/clear bit
1=Clear BERR status 0=Do nothing
SFENA 8 Enables generation of VME SYSFAIL upon
WDT timeout
1= Enable SYSFAIL generation 0=Disable Unused 9 Not Used
BPENA 10 Endian conversion bypass bit
1=Bypass 0=Not bypassed
ECENA 11 Endian conversion bit
1= Enabled 0=Disabled
Unused 31:12 Not Used
VBAR 0x04
VME_ADDR All Latched VME Address
VBAM 0x08
VME_ADDR 5:0 Latched VME Address Modifier
Unused 31:6 Not Used
