EMERSON KJ3201X1-BA1控制器
通过将“0”写入适当的“timer x Caused IRQ”字段，可以清除特定的定时器中断。或者，写入适当的Timer x IRQ Clear（TxIC）寄存器也将清除中断。使用“Timer x Caused IRQ”（定时器x引起的IRQ）字段清除中断时，请注意，确保使用正确的位掩码，以免影响其他寄存器设置非常重要。清除中断的首选方法是使用下面描述的“Timer x IRQ Clear”寄存器。计时器控制状态寄存器2（TCSR2）计时器也由位于BAR2地址偏移0x04处的计时器控制状态暂存器2（TCSR 2）中的位控制。该寄存器中的位映射如下：“读锁存选择”位用于选择可编程定时器的锁存模式（参见上文“定时器”部分）。如果该位设置为“0”，则每个定时器输出在读取其任何一个地址时被锁存。例如，对TMRCCR12寄存器的读取锁存计时器1和2的计数。对TMRCCR3寄存器的读取锁存定时器3的计数。对于这些寄存器中的任何一个的每次读取，都会继续执行此操作。
A particular timer interrupt can be cleared by writing a “0” to the appropriate “Timer
x Caused IRQ” field. Alternately, a write to the appropriate Timer x IRQ Clear (TxIC)
register will also clear the interrupt. When clearing the interrupt using the “Timer x
Caused IRQ” fields, note that it is very important to ensure that a proper bit mask is
used so that other register settings are not affected. The preferred method for clearing
interrupts is to use the “Timer x IRQ Clear” registers described below.
Timer Control Status Register 2 (TCSR2)
The timers are also controlled by bits in the Timer Control Status Register 2 (TCSR2)
located at offset 0x04 from the address in BAR2. The mapping of the bits in this
register are as follows:The “Read Latch Select” bit is used to select the latching mode of the programmable
timers (See “Timers” section above). If this bit is set to “0”, then each timer output is
latched upon a read of any one of its address. For example, a read to the TMRCCR12
register latches the count of timers 1 and 2. A read to the TMRCCR3 register latches
the count of timer 3. This continues for every read to any one of these registers.
