IS200JPDBG1A工控备件模块
访问可编程设备以在三个主处理器之间同步、传输、表决和比较数据。如果出现不一致，则以三个表中的两个表中找到的信号值为准，并相应地纠正第三个表。由采样定时变化引起的一次差异与不同数据的模式不同。每个主处理器在本地存储器中保存有关必要校正的数据。Tricon控制器内置故障分析仪例程在扫描结束时标记并使用任何差异，以确定特定模块上是否存在故障。主处理器将校正后的数据输入控制程序。32位主微处理器与相邻的主处理器模块并行执行控制程序。控制程序根据内置于控制程序中的用户定义的规则生成基于输入值表的输出值表。每个主处理器上的I/O处理器通过I/O总线管理输出数据到输出模块的传输。使用输出值表，I/O处理器生成较小的表，每个表对应于系统中的单个输出模块。每个小表通过I/O总线传输到相应输出模块的适当通道。例如，主处理器A通过I/O总线A将适当的表传输到每个输出模块的通道A。输出数据的传输优先于所有I/O模块的例行扫描。I/O处理器使用支持广播机制的通信总线管理主处理器和通信模块之间交换的数据。主处理器从主机箱中的双电源模块和电源导轨接收电源。一个电源模块或电源导轨上的故障不会影响系统性能。操作理论7 Tricon v9–v10系统3008型规划和安装指南3008型主处理器具有16兆DRAM（无备用电池）和32兆SRAM（有备用电池）。图3 3008型主处理器3006型和3007型主处理器的架构3006型与3007型可用于Tricon v9.0至v9.5.x系统。除了SRAM（3006为2兆字节，3007为1兆字节）之外，它们具有相同的架构和规格。图4 3006或3007型主处理器共享存储器128K Modbus（DB9）诊断读取（DB25）时钟/32 KB NVRAM主处理器MPC860A DRAM 16 MB DRAM 16 MBFLASH 6 MB TriBus FPGA TriBus（至其他MPS）上流上流下流双电源轨I/O和通信处理器MPC860B双电源调节器网络（RJ-45）+3.3伏+5伏32位总线32位总线故障容错I/O总线375 Kbaud诊断总线（至其他MPS）保留供将来使用上行下行I/O模块通信总线2 Mbaud通信模块故障检测电路定时发生器中断控制器主处理器NS32GX32调试通信端口DMA双端口RAM双端口RAM TRIBUS状态指示器双电源调节器+5VDC上行下行容错通信总线容错I/O总线IOC处理器内部系统总线双电源导轨512 KB EPROM 2 MB SRAM IOP处理器上下游浮点处理器NS32381 8第1章Tricon v9–v10系统总线系统和电源分配的规划和安装指南此图描述了蚀刻在机箱背板上的三个三重总线系统：TriBus、，I/O总线和通信总线。图5 Tricon总线系统和配电TriBus操作TriBus由三个独立的串行链路组成，在扫描开始时同步主处理器，并执行以下任一功能：•传输I/O、诊断和通信数据。•比较数据并标记上一次扫描中输出或内存数据的差异。Tricon控制器架构的一个重要特点是使用单个发射机向上游和下游主处理器发送数据，从而确保上游处理器和下游处理器接收到相同的数据。典型逻辑插槽左I/O模块*右I/O模块*主处理器A、B和C三总线双电源导轨通道C通道B通道A通道C通道C通道A通道B通道B通信模块ELCO I/O终端电源端子排2345端子排#1端子排#2通信总线I/O总线*左模块或右模块功能
access programmable device to synchronize, transmit, vote and compare data among the three Main Processors. If a disagreement occurs, the signal value found in two out of three tables prevails, and the third table is corrected accordingly. One-time differences which result from sample timing variations are distinguished from a pattern of differing data. Each Main Processor maintains data about necessary corrections in local memory. Any disparity is flagged and used at the end of the scan by the Tricon controller built-in fault analyzer routines to determine whether a fault exists on a particular module. The Main Processors put corrected data into the control program. The 32-bit main microprocessor executes the control program in parallel with the neighboring Main Processor modules. The control program generates a table of output values which are based on the table of input values according to customer-defined rules built into the control program. The I/O Processor on each Main Processor manages the transmission of output data to the output modules by means of the I/O bus. Using the table of output values, the I/O Processor generates smaller tables, each corresponding to an individual output module in the system. Each small table is transmitted to the appropriate channel of the corresponding output module over the I/O bus. For example, Main Processor A transmits the appropriate table to Channel A of each output module over I/O Bus A. The transmittal of output data has priority over the routine scanning of all I/O modules. The I/O Processor manages the data exchanged between the Main Processors and the communication modules using the communication bus which supports a broadcast mechanism. Main Processors receive power from dual Power Modules and power rails in the Main Chassis. A failure on one Power Module or power rail does not affect system performance. Theory of Operation 7 Planning and Installation Guide for Tricon v9–v10 Systems Model 3008 Main Processors Model 3008 has 16 megabytes DRAM (without battery back-up) and 32 kilobytes SRAM (with battery back-up). Figure 3 Architecture of a Model 3008 Main Processor Model 3006 and 3007 Main Processors Models 3006 and 3007 can be used with Tricon v9.0 to v9.5.x systems. They have the same architecture and specifications, except for SRAM, which is 2 megabytes for the 3006 and 1 megabyte for the 3007. Figure 4 Architecture of a Model 3006 or 3007 Main Processor Shared Memory 128K Modbus (DB9) Diag Read (DB25) Clock/ 32 KB NVRAM Main Processor MPC860A DRAM 16 MB DRAM 16 MB FLASH 6 MB TriBus FPGA TriBus (to other MPS) Up Stream Up Stream Down Stream Down Stream Dual Power Rails I/O & Comm Processor MPC860A Dual-Power Regulators Network (RJ-45) +3.3 Volts +5 Volts 32-Bit Bus 32-Bit Bus Fault Tolerant I/O Bus 375 Kbaud Diag Bus (to other MPS) Reserved for future use Up Stream Down Stream I/O Modules Comm Bus 2 Mbaud Communication Modules Failure Detect Circuitry Timing Generator Interrupt Controller Main Processor NS32GX32 Debug Comm Port DMA Dual Port RAM Dual Port RAM TRIBUS Status Indicators Dual Power Regulators +5VDC Up Stream Down Stream Fault-Tolerant Communication Bus Fault-Tolerant I/O Bus IOC Processor Internal System Bus Dual Power Rails 512 KB EPROM 2 MB SRAM IOP Processor Up Stream Down Stream Floating Point Processor NS32381 8 Chapter 1 Introduction Planning and Installation Guide for Tricon v9–v10 Systems Bus Systems and Power Distribution This figure depicts the three triplicated bus systems which are etched on the chassis backplane: the TriBus, the I/O bus, and the communication bus. Figure 5 Tricon Bus Systems and Power Distribution TriBus Operation The TriBus consists of three independent serial links which synchronizes the Main Processors at the beginning of a scan, and performs either of these functions: • Transfers I/O, diagnostic, and communication data. • Compares data and flags disagreements of output or memory data from the previous scan. An important feature of Tricon controller architecture is the use of a single transmitter to send data to both the upstream and downstream Main Processors which ensures the same data is received by the upstream processor and downstream processor. Typical Logical Slot Left I/O Module * Right I/O Module * Main Processors A, B, & C TriBus Dual Power Rails Channel C Channel B Channel A Channel C Channel B Channel A Communication Module ELCO Connectors for I/O Termination Power Terminal Strip 2345 Terminal Strip #1 Terminal Strip #2 Comm Bus I/O Bus * Either the left module or right module functions
