IS200ISBDG1AAA/IS200DAMDG2AAA模块备件
TMRCCR3和TMRCCR4寄存器不锁存新的计数值，允许获得同一实例中所有计时器的计数。定时器1和2加载计数寄存器（TMLCR12）定时器1和定时器2为16位宽，并从定时器1和2中加载计数寄存器中获取其加载计数（TMRLCR12），该寄存器位于BAR2中地址的偏移0x10处。此寄存器中的位映射如下：当这些字段中的任一字段被写入（通过单个32位写入或单独的16位写入）时，无论计时器是启用还是禁用，都会在计时器时钟的下一个上升沿加载写入值。存储在该寄存器中的值也会在计时器的终端计数（或超时）时自动重新加载。计时器3加载计数寄存器（TMRLCR3）计时器3为32位宽，并从计时器3加载计数器寄存器（TMLCR3）获得其加载计数，该寄存器位于BAR2中地址的偏移0x14处。此寄存器中的位映射如下：写入此字段时，无论计时器是启用还是禁用，计时器3都会在计时器时钟的下一个上升沿加载写入值。存储在该寄存器中的值也会在计时器的终端计数（或超时）时自动重新加载。字段位读或写计时器2加载计数TMRLCR12[31..16]R/W计时器1加载计数TMRL CR12[15..0]R/W字段位读/写计时器3加载计数TMRLCR3[31..0]R/W60 3 VMIVME-7750产品手动计时器4加载计数寄存器（TMRLCR4）计时器4为32位宽，并从位于BAR2中地址偏移0x18处的计时器4加载计数器寄存器（TMLCR4）获取其加载计数。此寄存器中的位映射如下：写入此字段时，无论计时器是启用还是禁用，计时器4都会在计时器时钟的下一个上升沿加载写入值。存储在该寄存器中的值也会在计时器的终端计数（或超时）时自动重新加载。计时器1和2电流计数寄存器（TMRCCR12）计时器1和计时器2的当前计数可通过计时器1和定时器2电流计数计数器（TMRCCR 12）读取，该寄存器位于BAR2中地址的偏移0x20处。该寄存器中的位映射如下：当读取任一字段时，当前计数值被锁存并返回。根据WDT控制状态寄存器（CSR2）中“读取锁存选择”位的设置，有两种模式决定如何锁存计数。有关这两种模式的更多信息，请参阅CSR2寄存器说明。定时器3电流计数寄存器（TMRCCR3）定时器3的电流计数可通过定时器3电流计数器寄存器（TMRC-CR3）读取，该寄存器位于BAR2中地址的偏移0x24处。此寄存器中的位映射如下：Field bits Read or Write Timer 4 Load Count TMLCR4[31..0]R/W Field bits Reador Write Timer 2 Count TMRCCR12[31..16]R.O.Timer 1 Count TMRCCR 12[15..0]R.O.Field bits Read or Write定时器3 Count TMLCR3[31..0]R.O.61 Timers 3读取此字段时，锁存并返回当前计数值。根据WDT控制状态寄存器（CSR2）中“读取锁存选择”位的设置，有两种模式决定如何锁存计数。有关这两种模式的更多信息，请参阅CSR2寄存器说明。定时器4电流计数寄存器（TMRCCR4）定时器4的电流计数可通过定时器4电流计数器寄存器（TMRC-CR4）读取，该寄存器位于BAR2中地址的偏移量0x28处。此寄存器中的位映射如下：读取此字段时，当前计数值为
TMRCCR3 and TMRCCR4 registers do not latch new count values, allowing the count of all timers at the same instance in time to be obtained. Timer 1 & 2 Load Count Register (TMRLCR12) Timers 1 & 2 are 16-bits wide and obtain their load count from the Timer 1 & 2 Load Count Register (TMRLCR12), located at offset 0x10 from the address in BAR2. The mapping of bits in this register are as follows: When either of these fields are written (either by a single 32-bit write or separate 16-bit writes), the respective timer is loaded with the written value on the next rising edge of the timer clock, regardless of whether the timer is enabled or disabled. The value stored in this register is also automatically reloaded on terminal count (or timeout) of the timer. Timer 3 Load Count Register (TMRLCR3) Timer 3 is 32-bits wide and obtains its load count from the Timer 3 Load Count Register (TMRLCR3), located at offset 0x14 from the address in BAR2. The mapping of bits in this register are as follows: When this field is written, Timer 3 is loaded with the written value on the next rising edge of the timer clock, regardless of whether the timer is enabled or disabled. The value stored in this register is also automatically reloaded on terminal count (or timeout) of the timer. Field Bits Read or Write Timer 2 Load Count TMRLCR12[31..16] R/W Timer 1 Load Count TMRLCR12[15..0] R/W Field Bits Read or Write Timer 3 Load Count TMRLCR3[31..0] R/W 60 3 VMIVME-7750 Product Manual Timer 4 Load Count Register (TMRLCR4) Timer 4 is 32-bits wide and obtains its load count from the Timer 4 Load Count Register (TMRLCR4), located at offset 0x18 from the address in BAR2. The mapping of bits in this register are as follows: When this field is written, Timer 4 is loaded with the written value on the next rising edge of the timer clock, regardless of whether the timer is enabled or disabled. The value stored in this register is also automatically reloaded on terminal count (or timeout) of the timer. Timer 1 & 2 Current Count Register (TMRCCR12) The current count of timers 1 & 2 may be read via the Timer 1 & 2 Current Count Register (TMRCCR12), located at offset 0x20 from the address in BAR2. The mapping of bits in this register are as follows: When either field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes. Timer 3 Current Count Register (TMRCCR3) The current count of Timer 3 may be read via the Timer 3 Current Count Register (TMRCCR3), located at offset 0x24 from the address in BAR2. The mapping of bits in this register are as follows: Field Bits Read or Write Timer 4 Load Count TMRLCR4[31..0] R/W Field Bits Read or Write Timer 2 Count TMRCCR12[31..16] R.O. Timer 1 Count TMRCCR12[15..0] R.O. Field Bits Read or Write Timer 3 Count TMRCCR3[31..0] R.O. 61 Timers 3 When this field is read, the current count value is latched and returned. There are two modes that determine how the count is latched depending on the setting of the “Read Latch Select” bit in the WDT Control Status Register (CSR2). See the CSR2 register description for more information on these two modes. Timer 4 Current Count Register (TMRCCR4) The current count of Timer 4 may be read via the Timer 4 Current Count Register (TMRCCR4), located at offset 0x28 from the address in BAR2. The mapping of bits in this register are as follows: When this field is read, the current count value is
