IS200ISBEH1A工控模块备件
寄存器1（TCSR1）计时器通过位于BAR2地址偏移0x00处的计时器控制状态寄存器1（TCPR1）进行控制和监控。此寄存器中的位映射如下：字段位读取或写入计时器1导致IRQ TCSR1[0]R/W计时器1启用TCSR1[1]R/W计时器2 IRQ启用TCSR2[2]R/W计时器3时钟选择TCSR1[4..3]R/W计时器4导致IRQ TCPR1[8]R/W计时器5启用TCSR1[9]R/W计时器6 IRQ启用TCPR1[10]R/W定时器2时钟选择TCSR 1[12..11]R/W定时器3导致IRQ TSSR1[16]R/W计时器7】R/W Timer 3 IRQ Enable TCSR1[18]R/W Timeer 3 Clock Select TCSR1[20..19]R/W Timers 4 Caused IRQ TCSR1[25]R/W Timer 4 Enable TCSR1[25]R/W Timer 4 IRQ Enable TCPR1[26]R/W Timer4 Clock Select TCPR1[28..27]R/W Reserved All Other Bits R/W所有这些位在系统复位后默认为“0”。58 3 VMIVME-7750产品手册每个计时器都有一个可独立选择的时钟源，该时钟源由“计时器x时钟选择”字段中的位模式选择，如下所示：通过将“1”写入适当的“计时器x启用”字段，可以独立启用每个计时器。类似地，通过将“1”写入适当的“timer x IRQ Enable”字段，可以独立启用每个计时器产生的中断。如果中断由计时器产生，则可以通过读取“计时器x引起的IRQ”字段来确定中断源。如果字段设置为“1”，则相应的计时器导致中断。请注意，多个计时器可能会导致一次中断。因此，必须读取所有计时器的状态，以确保识别所有中断源。通过将“0”写入适当的“timer x Caused IRQ”字段，可以清除特定的定时器中断。或者，写入适当的Timer x IRQ Clear（TxIC）寄存器也将清除中断。使用“Timer x Caused IRQ”（定时器x引起的IRQ）字段清除中断时，请注意，确保使用正确的位掩码，以免影响其他寄存器设置非常重要。清除中断的首选方法是使用下面描述的“Timer x IRQ Clear”寄存器。计时器控制状态寄存器2（TCSR2）计时器也由位于BAR2地址偏移0x04处的计时器控制状态暂存器2（TCSR 2）中的位控制。该寄存器中的位映射如下：“读锁存选择”位用于选择可编程定时器的锁存模式（参见上文“定时器”部分）。如果该位设置为“0”，则每个定时器输出在读取其任何一个地址时被锁存。例如，对TMRCCR12寄存器的读取锁存计时器1和2的计数。对TMRCCR3寄存器的读取锁存定时器3的计数。对于这些寄存器中的任何一个的每次读取，都会继续执行此操作。作为时钟速率MSb LSb 2MHz 0 0 1MHz 0 1 500kHz 1 0 250kHz 1 1字段位读或写读锁存选择TCSR2[0]R/W保留所有其他位R/W所有这些位在系统复位后默认为“0”。59计时器3的结果，不可能在给定时间内捕获所有四个计时器的值。然而，通过将该位设置为“1”，所有四个定时器输出将仅在读取定时器1和2电流计数寄存器（TMRCCR12）时被锁存。因此，为了同时捕获所有四个计时器的当前计数，首先执行对TMRCCR12的读取（32位读取），然后读取TMRCCR3和TMRCCR4。第一次读取（到TMRCCR12寄存器）导致同时锁存所有四个定时器值。随后读取
Register 1 (TCSR1) The timers are controlled and monitored via the Timer Control Status Register 1 (TCSR1) located at offset 0x00 from the address in BAR2. The mapping of the bits in this register are as follows: Field Bits Read or Write Timer 1 Caused IRQ TCSR1[0] R/W Timer 1 Enable TCSR1[1] R/W Timer 1 IRQ Enable TCSR1[2] R/W Timer 1 Clock Select TCSR1[4..3] R/W Timer 2 Caused IRQ TCSR1[8] R/W Timer 2 Enable TCSR1[9] R/W Timer 2 IRQ Enable TCSR1[10] R/W Timer 2 Clock Select TCSR1[12..11] R/W Timer 3 Caused IRQ TCSR1[16] R/W Timer 3 Enable TCSR1[17] R/W Timer 3 IRQ Enable TCSR1[18] R/W Timer 3 Clock Select TCSR1[20..19] R/W Timer 4 Caused IRQ TCSR1[24] R/W Timer 4 Enable TCSR1[25] R/W Timer 4 IRQ Enable TCSR1[26] R/W Timer 4 Clock Select TCSR1[28..27] R/W Reserved All Other Bits R/W All of these bits default to “0” after system reset. 58 3 VMIVME-7750 Product Manual Each timer has an independently selectable clock source which is selected by the bit pattern in the “Timer x Clock Select” field as follows: Each timer can be independently enabled by writing a “1” to the appropriate “Timer x Enable” field. Similarly, the generation of interrupts by each timer can be independently enabled by writing a “1” to the appropriate “Timer x IRQ Enable” field. If an interrupt is generated by a timer, the source of the interrupt may be determined by reading the “Timer x Caused IRQ” fields. If the field is set to “1”, then the respective timer caused the interrupt. Note that multiple timers can cause a single interrupt. Therefore, the status of all timers must be read to ensure that all interrupt sources are recognized. A particular timer interrupt can be cleared by writing a “0” to the appropriate “Timer x Caused IRQ” field. Alternately, a write to the appropriate Timer x IRQ Clear (TxIC) register will also clear the interrupt. When clearing the interrupt using the “Timer x Caused IRQ” fields, note that it is very important to ensure that a proper bit mask is used so that other register settings are not affected. The preferred method for clearing interrupts is to use the “Timer x IRQ Clear” registers described below. Timer Control Status Register 2 (TCSR2) The timers are also controlled by bits in the Timer Control Status Register 2 (TCSR2) located at offset 0x04 from the address in BAR2. The mapping of the bits in this register are as follows: The “Read Latch Select” bit is used to select the latching mode of the programmable timers (See “Timers” section above). If this bit is set to “0”, then each timer output is latched upon a read of any one of its address. For example, a read to the TMRCCR12 register latches the count of timers 1 and 2. A read to the TMRCCR3 register latches the count of timer 3. This continues for every read to any one of these registers. As a Clock Rate MSb LSb 2MHz 0 0 1MHz 0 1 500kHz 1 0 250kHz 1 1 Field Bits Read or Write Read Latch Select TCSR2[0] R/W Reserved All Other Bits R/W All of these bits default to “0” after system reset. 59 Timers 3 result, it is not possible to capture the values of all four timers at a given instance in time. However, by setting this bit to “1”, all four timer outputs will be latched only on reads to the Timer 1 & 2 Current Count Register (TMRCCR12). Therefore, to capture the current count of all four timers at the same time, perform a read to the TMRCCR12 first (with a 32-bit read), followed by a read to TMRCCR3 and TMRCCR4. The first read (to the TMRCCR12 register) causes all four timer values to be latched at the same time. The subsequent reads to the
