IS200ISBEH2ABB工控模块系统备件
（PIRQx）线。该映射如第47页图2-1所示，定义见表2-5。无法修改每个设备上存在的设备PCI中断线（INTA到INTD）。表2-5 BIOS设备组件的PCI设备中断映射厂商ID设备ID CPU地址映射ID选择PCI IRQ仲裁请求线PCI到VME桥Tundra Universe IIB 0x10E3 0x0000 AD19 INTA REQ0定时器/SRAM FPGA VMIC专有0x114A 0x6504 AD20 INTE N/A PMC1 N/A N/A N/A AD31 INTC REQ2以太网控制器Intel 82559ER 0x8086 0x1209 AD22 INTB REQ1 PCI主机桥GMCH 0x80860x1130 N/A N/A不适用VGA控制器GMCH 0x8086 0x1132 N/A N/A不适用PCI-LPC桥接器ICH2 0x8086 0x2440 N/A N/A/A不适用于VGA控制器ICH2 0x806 0x2442 N/A不不适用于USB控制器#1 ICH2 0x8056 0x2443 N/A N/B不适用于SMBus控制器ICH2 0x8086 0x244 N/A不适合于LAN控制器ICH2 0x18086 0x2469 N/A不支持USB控制器#2 ICH2 0x8046 0x244B N/A不/PCI到集线器桥ICH2 0x8086 0x244B不适用不适用47中断2图2-1 PC中断逻辑控制器8259 MASTER的连接-端口$020-$021 IRQ0 IRQ1 IRQ2 IRQ4 IRQ5 IRQ7 Universe IIB INTA PCI Interrupt IRQ3 IRQ6 CPU INTR Connections MAPPED BY BIOS PMC站点#1 BRIDGE b u s Timer Keybd Com 2 Com 1未使用的软盘控制中断8-15未使用的实时时钟鼠标数学AT Flash Hard Drv NA Coproc PIRQA PIRQB PIRQC PIRQD IRQ2 INTBINTC INTD MAPPER 8259 SLAVE-PORTS$0A0-$0A1 I/O控制器集线器ICH2 INT驱动PCI到VME总线以太网INT PIRQE IRQ8 IRQ9 IRQ10 IRQ11 IRQ13 IRQ12 IRQ14 IRQ15 FPGAINT 82559ER定时器/SRAM V M E 48 2 VMIVME-7750产品手册PCI-VME桥接器能够通过PCI SERR#线生成不可屏蔽中断（NMI）。表2-6描述了NMI使用的寄存器位。SERR中断通过逻辑路由回CPU上的NMI输入线。CPU读取NMI状态控制寄存器以确定NMI源（位设置为1）。在NMI中断例程处理中断后，软件通过将相应的启用/禁用位设置为1来清除NMI状态位。NMI启用和实时时钟寄存器可以屏蔽NMI信号并禁用/启用所有NMI源。表2-6 NMI寄存器位描述状态控制寄存器（I/O地址$061，读/写，只读）位7 SERR#NMI源状态（只读）-如果系统板代理检测到系统板错误，则此位设置为1。然后断言PCI SERR#线。要重置中断，请将Bit 2设置为0，然后将其设置为1。写入端口$061时，位7必须为0。Bit 2 PCI SERR#启用（读/写）-1=清除和禁用，0=启用启用和实时时钟地址寄存器（I/O地址$070，仅写）Bit 7 NMI启用-1=禁用，0＝启用49个集成外设2个集成外设VMIVME-7750包含国家半导体超级I/O（SIO）芯片。SIO为VMIVME-7750提供标准软盘驱动器控制器、两个16550 UART兼容串行端口、键盘和鼠标端口以及用于系统监控功能的通用I/O。两个串行端口信号均可从前面板获得。软盘信号可通过VME背板连接器获得，并可通过适当的转换实用程序板（VMIACC-0562）访问。IDE接口由Intel I/O控制器集线器（ICH2）芯片提供。IDE接口支持两个通道，即主通道和辅助通道。辅助通道在板上路由到可选的小型闪存插座。主通道从VME背板引出至VMIACC-0562过渡实用板，该板终止于标准的40针插头。该通道可以支持两个驱动器，一个主驱动器和一个从驱动器。VMIVME-7750上的IDE接口支持ATA-33、ATA-66和ATA-100驱动器，并根据使用的驱动器类型自动确定正确的操作模式。为了在ATA-100模式下正常工作，必须使用特殊的80芯电缆，而不是标准的40芯电缆。
(PIRQx) lines of the ICH2. This mapping is illustrated in Figure 2-1 on page 47 and is defined in Table 2-5. The device PCI interrupt lines (INTA through INTD) that are present on each device cannot be modified. Table 2-5 PCI Device Interrupt Mapping by the BIOS DEVICE COMPONENT VENDOR ID DEVICE ID CPU ADDRESS MAP ID SELECT PCI IRQ Arbitration Request Line PCI-to-VME Bridge Tundra Universe IIB 0x10E3 0x0000 AD19 INTA REQ0 Timer/SRAM FPGA VMIC Proprietary 0x114A 0x6504 AD20 INTE N/A PMC1 N/A N/A N/A AD31 INTC REQ2 Ethernet Controller Intel 82559ER 0x8086 0x1209 AD22 INTB REQ1 PCI Host Bridge GMCH 0x8086 0x1130 N/A N/A N/A VGA Controller GMCH 0x8086 0x1132 N/A N/A N/A PCI-LPC Bridge ICH2 0x8086 0x2440 N/A N/A N/A VGA Controller ICH2 0x8086 0x2442 N/A N/A N/A USB Controller #1 ICH2 0x8086 0x2443 N/A N/A N/A SMBus Controller ICH2 0x8086 0x2444 N/A N/A N/A LAN Controller ICH2 0x8086 0x2449 N/A N/A N/A USB Controller #2 ICH2 0x8086 0x244B N/A N/A N/A PCI-to-Hub Bridge ICH2 0x8086 0x244B N/A N/A N/A 47 Interrupts 2 Figure 2-1 Connections for the PC Interrupt Logic Controller 8259 MASTER- PORTS $020-$021 IRQ0 IRQ1 IRQ2 IRQ4 IRQ5 IRQ7 Universe IIB INTA PCI INTERRUPT IRQ3 IRQ6 CPU INTR CONNECTIONS MAPPED BY BIOS PMC Site #1 BRIDGE b u s Timer Keybd Com 2 Com 1 Unused Floppy Control Interrupt 8-15 Unused Real-Tm Clock Mouse Math AT Flash Hard Drv NA NA Coproc PIRQA PIRQB PIRQC PIRQD IRQ2 INTB INTC INTD MAPPER 8259 SLAVE- PORTS $0A0-$0A1 I/O Controller Hub ICH2 INT Drive PCI-to-VME Bus Ethernet INT PIRQE IRQ8 IRQ9 IRQ10 IRQ11 IRQ13 IRQ12 IRQ14 IRQ15 FPGAINT 82559ER Timers/SRAM V M E 48 2 VMIVME-7750 Product Manual The PCI-to-VME Bridge has the capability of generating a Non-Maskable Interrupt (NMI) via the PCI SERR# line. Table 2-6 describes the register bits that are used by the NMI. The SERR interrupt is routed through logic back to the NMI input line on the CPU. The CPU reads the NMI Status Control register to determine the NMI source (bits set to 1). After the NMI interrupt routine processes the interrupt, software clears the NMI status bits by setting the corresponding enable/disable bit to 1. The NMI Enable and Real-Time Clock register can mask the NMI signal and disable/enable all NMI sources. Table 2-6 NMI Register Bit Descriptions Status Control Register (I/O Address $061, Read/Write, Read Only) Bit 7 SERR# NMI Source Status (Read Only) - This bit is set to 1 if a system board agent detects a system board error. It then asserts the PCI SERR# line. To reset the interrupt, set Bit 2 to 0 and then set it to 1. When writing to port $061, Bit 7 must be 0. Bit 2 PCI SERR# Enable (Read/Write) - 1 = Clear and Disable, 0 = Enable Enable and Real-Time Clock Address Register (I/O Address $070, Write Only) Bit 7 NMI Enable - 1 = Disable, 0 = Enable 49 Integrated Peripherals 2 Integrated Peripherals The VMIVME-7750 incorporates a National Semiconductor Super I/O (SIO) chip. The SIO provides the VMIVME-7750 with a standard floppy drive controller, two 16550 UART-compatible serial ports, keyboard and mouse ports and general purpose I/O for system monitoring functions. Both serial port signals are available from the front panel. The floppy signals are available via the VME backplane connectors and can be accessed with the appropriate transition utility board (VMIACC-0562). The IDE interface is provided by the Intel I/O Controller Hub (ICH2) chip. The IDE interface supports two channels known as the primary and secondary channels. The secondary channel is routed on-board to the optional compact flash socket. The primary channel is routed out the VME backplane to a VMIACC-0562 transition utility board which terminates into a standard 40-pin header. This channel can support two drives, a master and slave. The IDE interface on the VMIVME-7750 supports ATA-33, ATA-66 and ATA-100 drives and automatically determines the proper operating mode based on the type of drive used. In order to properly function in the ATA-100 mode, a special 80 conductor cable must be used instead of the standard 40 conductor cable.
