IS200IGPAG2AED模块备件,DCS工控模块备件
必须能够同时监视系统中每个具有独占访问能力的主机的至少一个地址位置。未定义独占访问监视器在系统中的位置。然而，它必须被定位为能够观察到对用于独占访问序列的所有地址位置的访问。例如，如果系统包括多个内存控制器，则所有访问都通过包含独占访问监视器的中心点进行路由，或者每个内存控制器都需要单独的独占访问监视器。不要求系统支持对所有地址位置的独占访问序列。为访问不支持独占访问序列的位置提供了故障安全机制。通常，预期系统将支持对主存储器的独占访问序列，但不支持对任何外围设备的独占访问。8独占传输8.3独占访问信令8-72版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 8.3独占访问信令与独占传输相关的附加信号为：HEXCL独占传输。指示传输是独占访问序列的一部分。该信号是地址相位信号，并且具有与HADDR相同的有效性约束。HMASTER[m:0]主标识符。具有多个支持独占的线程的主机必须生成此信号以区分线程。主机生成的HMASTER值将与互连生成的值相结合，以确保呈现给独占访问监视器的结果HMASTER的值是唯一的。该信号是地址相位信号，并且具有与HADDR相同的有效性约束。HEXOKAY独家好的。添加额外的响应信号以指示独占传输的成功或失败。HMASTER[m:0]信号的宽度是执行定义的。但是，本规范建议使用以下宽度：•对于主组件，实现所支持的具有独占功能的线程数所需的位数。•对于主设备连接的互连端口，实现4位。可选地，互连可以支持更大位宽的配置。•对于从属或监视器组件，实现8位。可选地，从属或监视组件可以支持更大位宽的配置。HMASTER信令允许用于专用传输以外的目的。允许系统中的互连组件和从属组件使用该信令来区分系统中的不同主机，并适当地调整它们的行为。因此，必须为所有转账提供有效的HMASTER指示，而不仅仅是独家转账。8.3.1响应信号HEXOKAY信号用于指示独占传输的成功或失败：•断言时，HEXOKAI表示独占传输已成功，对于独占写入传输，存储器位置已更新。•当取消确认HEXOKAY时，表示独占传输失败。这可能是因为：-试图向不支持独占传输的地址位置进行独占传输。-独占写入传输失败，因为自匹配的独占读取传输以来，内存位置没有保持不变。在这种情况下，不会更新内存位置。主机可以通过确保总是首先执行到不支持独占传输的地址位置的独占读取传输，来确保它不会尝试执行到该位置的独占写入传输。以下约束适用于HEXOKAY：•HEXOKAI只能在断言HREADY的同一周期内断言。•不得在断言HRESP的同一周期中断言HEXOKAY。8独占传输8.4独占传输限制ARM IHI 0033B.b版权所有ARM
must be capable of concurrently monitoring at least one address location for each Exclusive access capable master in the system. The position of the Exclusive Access Monitor in the system is not defined. However, it must be positioned such that it can observe accesses to all address locations that are used for Exclusive access sequences. For example, if a system includes multiple memory controllers, either all accesses are routed through a central point that contains the Exclusive Access Monitor or a separate Exclusive Access Monitor is required at each memory controller. It is not required that a system supports an Exclusive access sequence to all address locations. A fail-safe mechanism is provided for accesses to locations that do not support an Exclusive access sequence. Typically, it would be expected that a system would support Exclusive access sequences to main memory, but not to any peripheral device. 8 Exclusive Transfers 8.3 Exclusive access signaling 8-72 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 8.3 Exclusive access signaling The additional signals associated with Exclusive Transfers are: HEXCL Exclusive Transfer. Indicates that the transfer is part of an Exclusive access sequence. This signal is an address phase signal and has the same validity constraints as HADDR. HMASTER[m:0] Master Identifier. A master that has multiple Exclusive capable threads must generate this signal to differentiate between the threads. The HMASTER value generated by the master will be combined with an interconnect generated value to ensure the resultant HMASTER value presented to the Exclusive Access Monitor is unique. This signal is an address phase signal and has the same validity constraints as HADDR. HEXOKAY Exclusive Okay. An additional response signal is added to indicate the success or failure of an Exclusive Transfer. The width of the HMASTER[m:0] signal is IMPLEMENTATION DEFINED. However, this specification recommends the following widths: • For master components, implement the number of bits required for the number of Exclusive capable threads supported. • For an interconnect port where a master connects, implement 4-bits. Optionally, an interconnect can support a configuration of a larger bit width. • For a slave or monitor component, implement 8-bits. Optionally, a slave or monitor component can support a configuration of a larger bit width. HMASTER signaling is permitted to be used for purposes other than Exclusive Transfers. It is permitted for the interconnect and slave components in a system to use this signaling to distinguish between different masters in the system and adapt their behavior appropriately. Therefore, a valid HMASTER indication must be provided for all transfers, not only Exclusive Transfers. 8.3.1 Response signaling The HEXOKAY signal is used to indicate the success or failure of an Exclusive Transfer: • When asserted, HEXOKAY indicates that the Exclusive Transfer has been successful and for an Exclusive Write transfer the memory location has been updated. • When deasserted HEXOKAY indicates that the Exclusive Transfer has failed. This can be because either: — An Exclusive Transfer has been attempted to an address location that does not support Exclusive Transfers. — An Exclusive Write transfer has failed because the memory location has not remained unchanged since a matching Exclusive Read transfer. In this scenario the memory location is not updated. A master can ensure that it does not attempt to perform an Exclusive Write transfer to an address location that does not support Exclusive Transfers by ensuring that it always performs an Exclusive Read transfer to that location first. The following constraints apply to HEXOKAY: • HEXOKAY must only be asserted in the same cycle as HREADY is asserted. • HEXOKAY must not be asserted in the same cycle as HRESP is asserted. 8 Exclusive Transfers 8.4 Exclusive Transfer restrictions ARM IHI 0033B.b Copyright ARM
