IS200IHG1A工控模块卡件
在扩展传输中，当在不同的上升时钟边缘采样时，被描述为稳定的信号需要保持在相同的值。然而，这些信号可能会在时钟边缘后出现毛刺，返回到与之前驱动的值相同的值。注：当使用典型的合成设计流程时，可以观察到这种行为，其中输出多路复用器的控制信号可以在扩展传输期间改变，但它们导致使用相同的输出值。接口在时钟上升沿之间是否无故障，这是执行定义。AHB5定义Stable_Between_Clock属性。定义此属性是为了确定接口是否保证需要稳定的信号在时钟上升沿之间保持稳定。如果此属性为True，则可以保证需要稳定的信号在时钟上升沿之间保持稳定且无毛刺。如果此属性为False或未定义，则信号可能在时钟上升沿之间出现毛刺。7.1.2复位复位信号HRESETn是协议中唯一有效的低电平信号，是所有总线元件的主要复位。复位可以异步断言，但在HCLK上升沿之后同步解除断言。部件必须定义最小周期数，复位信号必须被断言，以确保部件被完全复位，输出处于所需的复位值。在复位期间，所有主机必须确保地址和控制信号处于有效电平，并且HTRANS[1:0]指示空闲。重置期间，所有从设备必须确保HREADYOUT为高。ARM IHI 0033B.b版权所有ARM Limited或其附属公司。保留所有权利。8-69 ID102715非保密第8章独家转让本章介绍了独家转让的概念。它包含以下部分：•第8-70页的简介。•第8-71页的专用访问监视器。•第8-72页的独占访问信令。•第8-73页的独家转让限制。8独家转让8.1简介8-70版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 8.1简介AHB5定义Exclusive_Transfers属性。此属性定义接口是否支持独占传输的概念。如果未定义此属性，则接口不支持独占传输。独占传输提供了一种支持信号量类型操作的机制。独占访问序列是来自单个主机的独占传输序列，使用以下步骤进行操作：1。从地址执行独占读取传输。2.计算要存储到该地址的新数据值，该值基于从独占读取获得的数据值。3.在独占读取和独占写入之间可以有其他非独占传输。4.使用新的数据值对同一地址执行“独占写入”传输：•如果自“独占读取”传输以来没有其他主机写入该位置，则“独占写入传输”成功并更新内存。•如果自“独占读取”传输之后另一个主机已写入该位置，则“独占写入”传输将失败，并且不会更新内存位置。5.对独占写入传输的响应指示传输是否成功或失败。此序列确保只有在存储到内存时，该位置仍保持用于计算要写入该位置的新值的相同值时，才会更新内存位置。如果“独占写入”传输失败，预计主机将重复整个“独占”访问序列。执行定义了在独占读取传输之后，同一主机对相同或重叠位置的更新是否会导致相关的独占写入传输成功或失败。8独占传输8.2独占访问监视器ARM IHI 0033B。b版权所有ARM Limited或其附属公司。保留所有权利。8-71 ID102715非机密8.2独占访问监视器需要独占访问监视器来支持独占访问序列，该监视器必须确定独占写入传输是否成功或失败。独占访问监视器
Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an extended transfer. However, it is possible that these signals can glitch after clock edges, returning to the same value as previously driven. Note It is possible to observe this behavior when using a typical synthesis design flow, where the control signals for an output multiplexor can change during an extended transfer, but they result in the same output value being used. It is IMPLEMENTATION DEFINED whether an interface is glitch free between rising clock edges. AHB5 defines the Stable_Between_Clock property. This property is defined to determine if an interface guarantees that signals that are required to be stable remain stable between rising clock edges. If this property is True, it is guaranteed that signals that are required to be stable remain stable and glitch free between rising clock edges. If this property is False, or is not defined, signals can glitch between rising clock edges. 7.1.2 Reset The reset signal, HRESETn, is the only active LOW signal in the protocol and is the primary reset for all bus elements. The reset can be asserted asynchronously, but is deasserted synchronously after the rising edge of HCLK. A component must define a minimum number of cycles for which the reset signal must be asserted to ensure that the component is fully reset and the outputs are at the required reset values. During reset all masters must ensure the address and control signals are at valid levels and that HTRANS[1:0] indicates IDLE. During reset all slaves must ensure that HREADYOUT is HIGH. ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 8-69 ID102715 Non-Confidential Chapter 8 Exclusive Transfers This chapter describes the concept of Exclusive Transfers. It contains the following sections: • Introduction on page 8-70. • Exclusive Access Monitor on page 8-71. • Exclusive access signaling on page 8-72. • Exclusive Transfer restrictions on page 8-73. 8 Exclusive Transfers 8.1 Introduction 8-70 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 8.1 Introduction AHB5 defines the Exclusive_Transfers property. This property defines whether an interface supports the concept of Exclusive Transfers. If this property is not defined then the interface does not support Exclusive Transfers. Exclusive Transfers provide a mechanism to support semaphore-type operations. An Exclusive access sequence is a sequence of Exclusive Transfers from a single master that operate using the following steps: 1. Perform an Exclusive Read transfer from an address. 2. Calculate a new data value to store to that address that is based on the data value obtained from the Exclusive Read. 3. Between the Exclusive Read and the Exclusive Write there can be other Non-exclusive transfers. 4. Perform an Exclusive Write transfer to the same address, with the new data value: • If no other master has written to that location since the Exclusive Read transfer, the Exclusive Write transfer is successful and updates memory. • If another master has written to that location since the Exclusive Read transfer, the Exclusive Write transfer is failed and the memory location is not updated. 5. The response to the Exclusive Write transfer indicates if the transfer was successful or if it failed. This sequence ensures that the memory location is only updated if, at the point of the store to memory, the location still holds the same value that was used to calculate the new value to be written to the location. If the Exclusive Write transfer fails, it is expected that the master will repeat the entire Exclusive access sequence. It is IMPLEMENTATION DEFINED whether an update of the same, or overlapping, location by the same master after an Exclusive Read transfer will cause the associated Exclusive Write transfer to succeed or fail. 8 Exclusive Transfers 8.2 Exclusive Access Monitor ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 8-71 ID102715 Non-Confidential 8.2 Exclusive Access Monitor An Exclusive Access Monitor is required to support an Exclusive access sequence and this monitor must determine if an Exclusive Write transfer succeeds or fails. The Exclusive Access Monitor
