IS200ISBBG1AAB模块控制器
响应正常。如果从设备提供ERROR响应，则主设备可以取消突发中的剩余传输。然而，这不是一个严格的要求，主设备可以在突发中继续剩余的传输。HWRITE HWDATA[31:0]数据（A）HADDR[31:0]A HCLK B HREADY T0 HRESP T1 T2 T3 T4 HTRANS[1:0]NONSEQ IDLE T5 OKAY OKAY ERROR ERROR OKAY5 Slave Response Signaling 5.1 Slave transfer responses 5-58版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 ARM IHI 0023B.b版权所有ARM Limited或其附属公司。保留所有权利。6-59 ID102715非机密第6章数据总线本章介绍数据总线。它包含以下部分：•第6-60页的数据总线。•第6-61页的结尾。•数据总线宽度见第6-65页。6数据总线6.1数据总线6-60版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 6.1数据总线实现AHB系统需要单独的读写数据总线。虽然建议的最小数据总线宽度指定为32位，但可以按照第6-65页数据总线宽度中的描述进行更改。数据总线描述如下：•HWDATA。•hr数据。•第6-61页的结尾。6.1.1 HWDATA主设备在写入传输期间驱动写入数据总线。如果传输被延长，则主机必须保持数据有效，直到传输完成，如HREADY HIGH所示。有关保持信号在多个周期内有效的详细信息，请参见第7-68页的时钟。对于比总线宽度窄的传输，例如32位总线上的16位传输，主机只需驱动适当的字节通道。从设备从正确的字节通道中选择写入数据。请参阅第6-61页的Endianness，了解小端和大端系统中活动的字节通道的详细信息。6.1.2 HRDATA在读取传输期间，适当的从设备驱动读取数据总线。如果从设备通过保持HREADY LOW来扩展读取传输，则从设备只需在传输的最后周期中提供有效数据，如HREADY HIGH所示。对于比总线宽度窄的传输，从设备只需要在活动字节通道上提供有效数据。主机从正确的字节通道中选择数据。当传输完成时，从设备仅需提供有效数据，并发出OKAY响应。错误响应不需要有效的读取数据。6数据总线6.2 Endianness ARM IHI 0033B。b版权所有ARM Limited或其附属公司。保留所有权利。6-61 ID102715非机密6.2 Endianness AHB支持大端和小端系统。支持两种大端数据存储方法。AHB5引入Endian属性来定义支持哪种形式的大端数据访问。BE8字节不变大端。“字节不变大端序”一词源自这样一个事实，即字节访问（8位）使用的数据总线位与对同一地址的小端序访问相同。BE32字不变的大尾数。术语“字不变大端序”源自这样一个事实，即字访问（32位）使用最高有效（MS）和最低有效（LS）字节的相同数据总线位作为对相同地址的小端序访问。有关字节不变大端的更多信息，请参见第6-63页字节不变一节。下面的一组等式定义了哪些数据位用于小端序、字节不变的大端序和字不变的大尾序访问。方程式使用以下变量：address传输的地址。这些传输使用术语字节不变的数据。当发生较大字节不变的大端数传输时，数据传输方式如下：•MS字节传输到传输地址。•递减的有效字节被传送到顺序递增的地址。注意这是字节不变的大端和小端组件之间的关键区别。6数据总线6.2 Endianness 6-62版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 6.2.3字不变大端元当字不变的大端元组件访问字节时，以下等式显示了使用的数据总线位：Address_Offset=地址–（INT（地址/数据总线字节））×data_bus_Bytes Word_Offset＝（INT）（地址偏移量/4）×4字节偏移量=地址偏移量–字偏移量数据在data上传输[（8×（字偏移量+3–字节偏移量））+7:8×（字抵消量+3–Byte_Offset）]对于32位总线，字偏移量将始终为零
with an OKAY response. If a slave provides an ERROR response then the master can cancel the remaining transfers in the burst. However, this is not a strict requirement and it is acceptable for the master to continue the remaining transfers in the burst. HWRITE HWDATA[31:0] Data (A) HADDR[31:0] A HCLK B HREADY T0 HRESP T1 T2 T3 T4 HTRANS[1:0] NONSEQ IDLE T5 OKAY OKAY ERROR ERROR OKAY 5 Slave Response Signaling 5.1 Slave transfer responses 5-58 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 6-59 ID102715 Non-Confidential Chapter 6 Data Buses This chapter describes the data buses. It contains the following sections: • Data buses on page 6-60. • Endianness on page 6-61. • Data bus width on page 6-65. 6 Data Buses 6.1 Data buses 6-60 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 6.1 Data buses Separate read and write data buses are required to implement an AHB system. Although the recommended minimum data bus width is specified as 32-bits, this can be changed as described in Data bus width on page 6-65. The data buses are described in: • HWDATA. • HRDATA. • Endianness on page 6-61. 6.1.1 HWDATA The master drives the write data bus during write transfers. If the transfer is extended then the master must hold the data valid until the transfer completes, as indicated by HREADY HIGH. See Clock on page 7-68 for details on holding signals valid across multiple cycles. For transfers that are narrower than the width of the bus, for example a 16-bit transfer on a 32-bit bus, the master only has to drive the appropriate byte lanes. The slave selects the write data from the correct byte lanes. See Endianness on page 6-61 for details of the byte lanes that are active for a little-endian and big-endian system. 6.1.2 HRDATA The appropriate slave drives the read data bus during read transfers. If the slave extends the read transfer by holding HREADY LOW, then the slave only has to provide valid data in the final cycle of the transfer, as indicated by HREADY HIGH. For transfers that are narrower than the width of the bus, the slave is only required to provide valid data on the active byte lanes. The master selects the data from the correct byte lanes. A slave only has to provide valid data when a transfer completes with an OKAY response. ERROR responses do not require valid read data. 6 Data Buses 6.2 Endianness ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 6-61 ID102715 Non-Confidential 6.2 Endianness AHB supports both big-endian and little-endian systems. Two approaches to big-endian data storage are supported. AHB5 introduces the Endian property to define which form of big-endian data access is supported. BE8 Byte-invariant big-endian. The term, byte-invariant big-endian, is derived from the fact that a byte access (8-bit) uses the same data bus bits as a little-endian access to the same address. BE32 Word-invariant big-endian. The term, word-invariant big-endian, is derived from the fact that a word access (32-bit) uses the same data bus bits for the Most Significant (MS) and the Least Significant (LS) bytes as a little-endian access to the same address. Additional information on byte-invariant big-endian can be found in the section Byte invariance on page 6-63. The following set of equations defines which data bits are used for little-endian, byte-invariant big-endian, and word- invariant big-endian accesses. The equations use the following variables: address The address of the transfer. Data he term byte-invariant is used for these transfers. When larger byte-invariant big-endian transfers occur, data is transferred such that: • The MS byte is transferred to the transfer address. • Decreasingly significant bytes are transferred to sequentially incrementing addresses. Note This is the key difference between byte-invariant big-endian and little-endian components. 6 Data Buses 6.2 Endianness 6-62 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 6.2.3 Word-invariant big-endian When a word-invariant big-endian component accesses a byte, the following equation shows which data bus bits are used: Address_Offset = Address –(INT(Address / Data_Bus_Bytes)) × Data_bus_Bytes Word_Offset = (INT(Address_Offset / 4)) × 4 Byte_Offset = Address_Offset – Word_Offset Data is transferred on DATA[(8 × (Word_Offset + 3 – Byte_Offset)) + 7 : 8 × (Word_Offset + 3 – Byte_Offset)] For a 32-bit bus, the Word_Offset will always be zero
