IS200ISBBG2A工控备件机器人模
地址区域的末端必须存在于1KB边界上。所有主机都设计为不在1KB地址边界上执行递增传输。这确保了突发不会越过地址解码边界。图4-1显示了解码器生成的HSELx从属选择信号。图4-1从机选择信号4.2.1默认从机如果系统设计不包含完全填充的存储器映射，则必须实施额外的默认从机，以在访问任何不存在的地址位置时提供响应。如果尝试向不存在的地址位置进行非顺序或顺序传输，则默认从设备提供错误响应。IDLE或BUSY传输到不存在的位置会导致零等待状态OKAY响应。4.2.2多从选择允许单个从接口支持多个从选择、HSELx信号。每个HSELx信号对应于高阶地址位的不同解码。这允许单个从接口提供多个逻辑接口，每个逻辑接口在系统地址映射中具有不同的位置。可分配给逻辑接口的最小地址空间为1KB。这种方法消除了从属设备支持地址解码以区分逻辑接口的需要。多个HSELx信号的典型用例是在地址映射中的不同位置具有其主数据路径和控制寄存器的外围设备。这两个位置都可以通过单个接口访问，而不需要从设备执行地址解码。主解码器HADDR[31:0]HSEL_S2从1从2从3 HSEL_S1 HSEL_S3 4总线互连4.3读取数据和响应多路复用器4-54版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 4.3读取数据和响应多路复用器AHB协议与读取数据多路复用器互连方案一起使用。主设备向所有从设备发出地址和控制信号，解码器选择合适的从设备。来自所选从设备的任何响应数据都通过读数据多路复用器传递到主设备。图4-2显示了实现具有三个从设备的设计所需的多路复用器互连结构。图4-2多路复用器互连注意：如果支持独占传输，多路复用器还必须将适当的HEXOKAY信号路由到主设备。主-从1解码器HRDATA[31:0]HADDR[31:0]HRESP_2从2从3 HRESP HREADY HREADYOUT_2 HRDATA_2 HRESP_1 HREADYOUT_1 HRDATA_1 HRESP_3 HREADYOUT _3 HRDATA_3 HREADY HREADY多路复用器X1 Y1 Z1 X2 Y2 Z2 X3 Y3 Z3 X Z ARM IHI 0033B。b版权所有ARM Limited或其附属公司。保留所有权利。5-55 ID102715非机密第5章从属响应信令本章描述从属响应信令。它包含以下部分：•第5-56页的从属传输响应。5从属响应信令5.1从属传输响应5-56版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 5.1从属传输响应在主设备开始传输后，从属设备控制传输的进度。主机无法在开始传输后取消传输。对于支持AHB5 Exclusive_Transfers属性的组件，请参阅第8-72页的Exclusive access signaling，以获取额外HEXOKAY传输响应信号的详细信息。从属设备必须提供一个响应，指示访问时的传输状态。传输状态由HRESP信号提供。表5-1列出了HRESP状态。表5-1显示了完整的传输响应是HRESP和HREADYOUT信号的组合。表5-2列出了基于HRESP和HREADYOUT信号状态的完整传输响应。这意味着从设备可以通过以下三种方式完成传输：•立即完成传输。•发出错误信号，表明传输失败。•插入一个或多个等待状态，以便有时间完成传输。这三个从属传输响应描述如下：•传输完成。•传输待定。•错误响应见第5-57页。5.1.1传输完成当HREADY为HIGH（高）且HRESP为OKAY（正常）时，会发出成功完成传输的信号。5.1.2传输挂起典型从设备使用HREADYOUT
the end of the address region must exist on a 1KB boundary. All masters are designed so that they do not perform incrementing transfers over a 1KB address boundary. This ensures that a burst never crosses an address decode boundary. Figure 4-1 shows the HSELx slave select signals generated by the decoder. Figure 4-1 Slave select signals 4.2.1 Default slave If a system design does not contain a completely filled memory map then an additional default slave must be implemented to provide a response when any of the nonexistent address locations are accessed. If a NONSEQUENTIAL or SEQUENTIAL transfer is attempted to a nonexistent address location then the default slave provides an ERROR response. IDLE or BUSY transfers to nonexistent locations result in a zero wait state OKAY response. 4.2.2 Multiple slave select A single slave interface is permitted to support multiple slave select, HSELx, signals. Each HSELx signal corresponds to a different decode of the higher order address bits. This permits a single slave interface to provide multiple logical interfaces, each with a different location in the system address map. The minimum address space that can be allocated to a logical interface is 1KB. This approach removes the need for a slave to support the address decode to differentiate between the logical interfaces. A typical use case for multiple HSELx signals is a peripheral that has its main data path and control registers at different locations in the address map. Both locations can be accessed through a single interface without the need for the slave to perform an address decode. Master Decoder HADDR[31:0] HSEL_S2 Slave 1 Slave 2 Slave 3 HSEL_S1 HSEL_S3 4 Bus Interconnection 4.3 Read data and response multiplexor 4-54 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 4.3 Read data and response multiplexor The AHB protocol is used with a read data multiplexor interconnection scheme. The master drives out the address and control signals to all the slaves, with the decoder selecting the appropriate slave. Any response data from the selected slave, passes through the read data multiplexor to the master. Figure 4-2 shows the multiplexor interconnection structure required to implement a design with three slaves. Figure 4-2 Multiplexor interconnection Note If Exclusive Transfers are supported, the multiplexor must also route the appropriate HEXOKAY signal to the master. Master Slave 1 Decoder HRDATA[31:0] HADDR[31:0] HRESP_2 Slave 2 Slave 3 HRESP HREADY HREADYOUT_2 HRDATA_2 HRESP_1 HREADYOUT_1 HRDATA_1 HRESP_3 HREADYOUT_3 HRDATA_3 HREADY HREADY HREADY Multiplexor X1 Y1 Z1 X2 Y2 Z2 X3 Y3 Z3 X Y Z ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 5-55 ID102715 Non-Confidential Chapter 5 Slave Response Signaling This chapter describes the slave response signaling. It contains the following section: • Slave transfer responses on page 5-56. 5 Slave Response Signaling 5.1 Slave transfer responses 5-56 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 5.1 Slave transfer responses After a master has started a transfer, the slave controls how the transfer progresses. A master cannot cancel a transfer after it has commenced. For components that support the AHB5 Exclusive_Transfers property, see Exclusive access signaling on page 8-72 for details of the additional HEXOKAY transfer response signal. A slave must provide a response that indicates the status of the transfer when it is accessed. The transfer status is provided by the HRESP signal. Table 5-1 lists the HRESP states. Table 5-1 shows that the complete transfer response is a combination of the HRESP and HREADYOUT signals. Table 5-2 lists the complete transfer response based on the status of the HRESP and HREADYOUT signals. This means the slave can complete the transfer in the following three ways: • Immediately complete the transfer. • Signal an error to indicate that the transfer has failed. • Insert one or more wait states to enable time to complete the transfer. These three slave transfer responses are described in: • Transfer done. • Transfer pending. • ERROR response on page 5-57. 5.1.1 Transfer done A successful completed transfer is signaled when HREADY is HIGH and HRESP is OKAY. 5.1.2 Transfer pending A typical slave uses HREADYOUT to
