IS200ISBDG1AAA IS200ISBDG1模块燃机电气卡件
插入此位表示传输是指令获取。HPROT[1]特权当断言时，此位表示传输是特权访问。当取消断言时，此位表示传输是非特权访问。HPROT[2]可缓冲如果两个HPROT[4:3]都被取消断言，则当该位为：•取消断言时，必须从最终目的地给出写入响应。•断言，可以从中间点给出写响应，但写传输需要在最终目的地及时可见。HPROT[3]可修改当断言时，可以修改传输的特性。取消断言后，不得修改传输特性。HPROT[4]查找当断言时，必须在缓存中查找传输。取消断言后，不需要在缓存中查找传输，传输必须传播到最终目的地。HPROT[5]分配当断言时，出于性能原因，本规范建议在缓存中分配此传输。由于性能原因，当取消断言时，本规范建议不在缓存中分配此传输。HPROT[6]可共享当断言时，表示此传输到与系统中其他主机共享的内存区域。在传输对其他主机可见之前，不得提供传输响应。取消断言时，表示此传输是不可共享的，并且内存区域未与系统中的其他主机共享。传输的响应不能保证传输对其他主机可见。3转让3.8内存类型3-46版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.8.1数据或指令所有传输都包括数据或指令保护位HPROT[0]：•断言时，此位表示传输是数据访问。•当取消断言时，此位表示传输是指令获取。协议将此指示定义为提示。它在所有情况下都不准确，例如，事务包含指令和数据项的混合。本规范建议主设备将HPROT[0]设置为HIGH，以指示数据访问，除非该访问被明确认为是指令访问。3.8.2无特权或特权所有传输都包括特权或无特权保护位HPROT[1]：•断言时，此位表示传输是特权访问。•当取消断言时，此位表示传输是非特权访问。注意：某些处理器支持多个权限级别，请参阅所选处理器的文档以确定到AHB权限级别的映射。提供的唯一区别是特权访问和非特权访问。3.8.3存储器类型本节提供了有关HPROT保护控制信号的附加信息，以及这些信号与不同存储器类型的关系。表3-6显示了HPROT[6:2]信号与存储器类型之间的映射。不允许表3-6中未显示的位组合。设备存储器类型E后缀表示允许早期写入响应。设备存储器类型nE后缀表示不允许早期写入响应，并且写入响应必须来自最终目的地。以下各节详细介绍了每种内存类型的要求。表3-6 HPROT[6:2]映射到内存类型HPROT[6]HPROT[5]HPROT[4]HPROT[3]HPROT[2]内存类型可共享分配查找可修改缓冲区0 0 0 0设备nE 0 0 0 1设备-E 0 0 1 0正常不可缓存、不可共享0 0或1 1 1 0直写、不可分享0 0或2 1 1回写、不共享1 0 0 1正常不可高速缓存、可共享1 0或1 2 1 0直读、，可共享1 0或1 1 1 1回写，可共享3传输3.8内存类型ARM IHI 0033B。b版权所有ARM Limited或其附属公司。保留所有权利。3-47 ID102715非机密3.8.4设备存储器要求对于所有设备存储器，即设备nE和设备E，要求的行为是：•必须从最终目的地获取读取数据。•转让不得拆分为多个转让或与其他转让合并。•读取不得预取或p
serted this bit indicates the transfer is an instruction fetch. HPROT[1] Privileged When asserted, this bit indicates the transfer is a privileged access. When deasserted this bit indicates the transfer is an unprivileged access. HPROT[2] Bufferable If both of HPROT[4:3] are deasserted then, when this bit is: • Deasserted, the write response must be given from the final destination. • Asserted, the write response can be given from an intermediate point, but the write transfer is required to be made visible at the final destination in a timely manner. HPROT[3] Modifiable When asserted, the characteristics of the transfer can be modified. When deasserted the characteristics of the transfer must not be modified. HPROT[4] Lookup When asserted, the transfer must be looked up in a cache. When deasserted, the transfer does not need to be looked up in a cache and the transfer must propagate to the final destination. HPROT[5] Allocate When asserted, for performance reasons, this specification recommends that this transfer is allocated in the cache. When deasserted, for performance reasons, this specification recommends that this transfer is not allocated in the cache. HPROT[6] Shareable When asserted, indicates that this transfer is to a region of memory that is shared with other masters in the system. A response for the transfer must not be provided until the transfer is visible to other masters. When deasserted, indicates that this transfer is Non-shareable and the region of memory is not shared with other masters in the system. A response for the transfer does not guarantee the transfer is visible to other masters. 3 Transfers 3.8 Memory types 3-46 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 3.8.1 Data or Instruction All transfers include the Data or Instruction protection bit HPROT[0]: • When asserted, this bit indicates the transfer is a data access. • When deasserted this bit indicates the transfer is an instruction fetch. The protocol defines this indication as a hint. It is not accurate in all cases, for example, where a transaction contains a mix of instruction and data items. This specification recommends that a master sets HPROT[0] HIGH, to indicate a data access unless the access is specifically known to be an instruction access. 3.8.2 Unprivileged or Privileged All transfers include the Privileged or Unprivileged protection bit, HPROT[1]: • When asserted, this bit indicates the transfer is a Privileged access. • When deasserted this bit indicates the transfer is an Unprivileged access. Note Some processors support multiple levels of privilege, see the documentation for the selected processor to determine the mapping to AHB privilege levels. The only distinction provided is between Privileged and Unprivileged access. 3.8.3 Memory type This section provides additional information on the HPROT Protection Control signals and how these signals relate to different memory types. Table 3-6 shows the mapping between HPROT[6:2] signaling and the memory type. Bit combinations that Table 3-6 does not show are not permitted. The Device memory type E suffix indicates that an early write response is permitted. The Device memory type nE suffix indicates that an early write response is not permitted and that the write response must come from the final destination. The following sections detail the requirements for each memory type. Table 3-6 HPROT[6:2] mapping to memory type HPROT[6] HPROT[5] HPROT[4] HPROT[3] HPROT[2] Memory Type Shareable Allocate Lookup Modifiable Bufferable 0 0 0 0 0 Device-nE 0 0 0 0 1 Device-E 0 0 0 1 0 Normal Non-cacheable, Non-shareable 0 0 or 1 1 1 0 Write-through, Non-shareable 0 0 or 1 1 1 1 Write-back, Non-shareable 1 0 0 1 0 Normal Non-cacheable, Shareable 1 0 or 1 1 1 0 Write-through, Shareable 1 0 or 1 1 1 1 Write-back, Shareable 3 Transfers 3.8 Memory types ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 3-47 ID102715 Non-Confidential 3.8.4 Device memory requirements For all Device memory, that is Device-nE and Device-E, the required behavior is: • Read data must be obtained from the final destination. • Transfers must not be split into multiple transfers or merged with other transfers. • Reads must not be prefetched or p
