IS200ISBDG1AAA/IS200DAMDG2AAA DCS模块卡件
图3-16:T0-T1主设备向地址a发起一个单脉冲串。T1-T2主设备向Y地址插入一个IDLE传输。从设备插入一个等待状态，HREADYOUT=LOW。T2-T3主机向地址Z插入一个IDLE传输。T3-T4主机将传输类型更改为NONSEQ，并启动向地址B的INCR4传输。直到HREADY变为HIGH，不允许再进行地址更改。T5-T6到地址A的单脉冲串以HREADY HIGH结束，并且主机开始到地址B的第一个节拍。T6-T7到地址B INCR4传输的第一个拍完成，并且主机启动到地址B+4的下一个节拍。HADDR[31:0]A HCLK Y HBURST[2:0]SINGLE HREADY B B+4 HRDATA[31:0]INCR4 HTRANS[1:0]NONSEQ IDLE NONSEQ数据（A）T0 T1 T2 T3 T4 T6 T7数据（B）INCR4 IDLE Z 3传输3.6等待传输ARM IHI 0033B。B版权所有ARM Limited或其附属公司。保留所有权利。3-43 ID102715非机密错误响应后在等待的传输过程中，如果从设备响应错误响应，则当HREADY为LOW时，允许主设备更改地址。有关ERROR响应的更多信息，请参阅第5-57页的ERROR响应。图3-17显示了一个等待的传输，地址在从设备的ERROR响应后发生变化。图3-17在图3-17:T0-T1中出现错误后，等待传输期间地址发生变化。主设备启动脉冲串的下一个节拍至地址0x24。T1-T3主设备将脉冲串的下一个节拍启动到地址0x28。从设备以OK（正常）响应。T3-T4从设备响应错误。T4-T5主机将传输类型更改为IDLE，并允许在HREADY为LOW时更改地址。从设备完成ERROR响应。T5-T6地址0xC0处的从机以OKAY响应。HADDR[31:0]0x24 HCLK 0x28 HBURST[2:0]INCR4 HREADY 0xC0 HTRANS[1:0]SEQ SEQ IDLE T0 T1 T2 T4 T5 T6 INCR4 HRESP OKAY OKAY ERROR ERROR OKAY3传输3.7保护控制3-44版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.7本规范的保护控制问题A定义了4位HPROT信号，本节对此进行了描述。本规范的B版增加了扩展内存类型，这在第3-45页的内存类型中有更详细的描述。注：HPROT[3]的名称在本规范第A版和第B版之间有所更改，但定义保持不变。在问题A中，HPROT[3]被指定为可缓存，在问题B中，被指定为可以修改。保护控制信号HPROT[3:0]提供了关于总线访问的附加信息，主要用于实现某种保护级别的任何模块。信号指示传输是否：•操作码获取或数据访问。•特权模式访问或用户模式访问。对于具有内存管理单元的主机，这些信号还指示当前访问是可缓存还是可缓冲。表3-4列出了HPROT信号编码。注：许多主机无法生成准确的保护信息。如果主机无法生成准确的保护信息，本规范建议：•主机将HPROT设置为0b0011，以对应于不可缓存、不可缓冲、特权的数据访问。•除非绝对必要，否则从属设备不使用HPROT。HPROT控制信号具有与地址总线完全相同的定时。然而，它们必须在整个突发传输过程中保持恒定。表3-4保护信号编码HPROT[3]可修改HPROT[2]可缓冲HPROT[1]特权HPROT[0]数据/操作码描述/-0操作码获取/-1数据访问/-0用户访问/-1特权访问/-0不可缓冲-1-可缓冲0-不可缓存1-可缓存3传输3.8内存类型ARM IHI 0033B.b版权所有ARM Limited或其附属公司。保留所有权利。3-45 ID102715非机密3.8内存类型AHB5定义Extended_Memory_types属性。此属性定义接口是否支持本节中描述的扩展内存类型。如果未定义此属性，则接口不支持扩展内存类型。本期规范增加了额外的HPROT信令，并为每种存储器类型提供了更详细的需求列表。表3-5显示了每个HPROT位的含义，第3-46页的表3-6提供了HPROT[6:2]和存储器类型之间的映射。表3-5 HPROT位的含义位名称描述HPROT[0]数据/仪器当断言时，该位表示传输是数据访问。当deasFigure 3-16: T0-T1 master sends a single pulse train to address a. The T1-T2 master device inserts an IDLE transmission to the Y address. Insert a waiting state from the device, HREADYOUT=LOW. T2-T3 host inserts an IDLE transmission to address Z. The T3-T4 host changes the transmission type to NONSEQ and starts the INCR4 transmission to address B. No address change is allowed until HREADY becomes HIGH. The monopulse train from T5-T6 to address A ends with HREADY HIGH, and the host starts to the first beat of address B. The first beat of T6-T7 transmission to address B INCR4 is completed, and the host starts to the next beat of address B+4. HADDR [31:0] A HCLK Y HBURST [2:0] SINGLE HREADY B B+4 HRDATA [31:0] INCR4 HTRANS [1:0] NONSEQ IDLE NONSEQ data (A) T0 T1 T2 T3 T4 T6 T7 data (B) INCR4 IDLE Z 3 transmission 3.6 Waiting for transmission ARM IHI 0033B. B Copyright ARM Limited or its affiliates. All rights reserved. 3-43 ID102715 In the waiting transmission process after the unclassified error response, if the slave device responds to the error response, when HREADY is LOW, the master device is allowed to change the address. For more information about ERROR responses, see ERROR Responses on page 5-57. Figure 3-17 shows a waiting transmission. The address changes after the slave's ERROR response. Figure 3-17 After an error occurs in Figure 3-17: T0-T1, the address changes while waiting for transmission. The next beat of the main equipment startup pulse train is to the address 0x24. The T1-T3 master device starts the next beat of the pulse train to the address 0x28. The slave responds with OK. T3-T4 slave response error. The T4-T5 host changes the transmission type to IDLE and allows the address to be changed when HREADY is LOW. The slave completes the ERROR response. The slave at T5-T6 address 0xC0 responds with OKAY. HADDR [31:0] 0x24 HCLK 0x28 HBURST [2:0] INCR4 HREADY 0xC0 HTRANS [1:0] SEQ IDLE T0 T1 T2 T4 T5 T6 INCR4 HRESP OKAY OKAY ERROR OKAY3 Transmission 3.7 Protection Control 3-44 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B. b Unclassified ID102715 3.7 The protection control problem A of this specification defines a 4-bit HPROT signal, which is described in this section. Version B of this specification adds extended memory types, which are described in more detail in the memory types on page 3-45. Note: The name of HPROT [3] has been changed between the A and B editions of this specification, but the definition remains unchanged. In question A, HPROT [3] is designated as cacheable, and in question B, it is designated as modifiable. The protection control signal HPROT [3:0] provides additional information about bus access, which is mainly used for any module to achieve a certain protection level. The signal indicates whether the transmission: • Opcode acquisition or data access. • Privileged mode access or user mode access. For hosts with memory management units, these signals also indicate whether the current access is cacheable or bufferable. Table 3-4 lists the HPROT signal codes. Note: Many hosts cannot generate accurate protection information. If the host cannot generate accurate protection information, this specification recommends that: • The host should set HPROT to 0b0011 to correspond to non cacheable, non cacheable, and privileged data access. • The slave does not use HPROT unless absolutely necessary. The HPROT control signal has exactly the same timing as the address bus. However, they must remain constant throughout the burst transmission process. Table 3-4 Protection signal code HPROT [3] can be modified HPROT [2] bufferable HPROT [1] privilege HPROT [0] data/opcode description/- 0 opcode acquisition/- 1 data access/- 0 user access/- 1 privileged access/- 0 non bufferable - 1 bufferable - 0 non bufferable - 1 bufferable - 3 transmission 3.8 memory type ARM IHI 0033B. b Copyright ARM Limited or its affiliates. All rights reserved. 3-45 ID102715 unclassified 3.8 Memory type AHB5 definition Extended_ Memory_ The types attribute. This property defines whether the interface supports the extended memory type described in this section. If this property is not defined, the interface does not support extended memory types. This specification adds additional HPROT signaling and provides a more detailed list of requirements for each memory type. Table 3-5 shows the meaning of each HPROT bit. Table 3-6 on page 3-46 provides the mapping between HPROT [6:2] and memory type. Table 3-5 Meaning bit name of HPROT bit describes HPROT [0] data/instrument. When asserting, this bit indicates that the transmission is data access. When deas
