IS200ISBEH1A工业卡件,ABB卡件
INCR8和INCR16。•WRAP4、WRAP8和WRAP16。图3-14显示了固定长度突发中的等待传输，传输类型从BUSY变为SEQ。图3-14等待传输，BUSY到SEQ用于固定长度突发图3-14:T0-T1主设备启动INCR4突发的下一个节拍至地址0x24。T1-T3主机向地址0x28插入BUSY传输。从机插入HREADYOUT=LOW的等待状态。T3-T4主控器将传输类型更改为SEQ，并将脉冲串的下一个节拍启动到地址0x28。T4-T6 HREADY LOW时，主机必须保持HTRANS恒定。T5-T6拍到地址0x24结束，HREADY HIGH。T6-T7到地址0x28的INCR4传输的第三个节拍完成，主机开始到地址0x2C的最后一个节拍。HADDR[31:0]0x24 HCLK 0x28 HBURST[2:0]INCR4 HREADY 0x28 0x2C HRDATA[31:0]INCR4 HTRANS[1:0]SEQ BUSY SEQ T0 T1 T2 T3 T4 T5 T6 T7 INCR4 INCR4数据（0x24）数据（0x28）3传输3.6等待传输ARM IHI 0033B.b版权所有ARM Limited或其附属公司。保留所有权利。3-41 ID102715非机密BUSY传输，未定义长度突发在等待传输未定义长度的突发INCR期间，当HREADY为LOW时，允许主机从BUSY转换为任何其他传输类型。如果执行了序列转移，则脉冲串继续，但如果执行了IDLE或NONSEQ转移，脉冲串终止。图3-15显示了未定义长度突发期间的等待传输，传输类型从BUSY变为NONSEQ。图3-15未定义长度突发的等待传输，BUSY到NONSEQ在图3-15:T0-T1中，主机启动INCR突发的下一个节拍至地址0x64。T1-T3主机向地址0x68插入BUSY传输。从机插入HREADYOUT=LOW的等待状态。T3-T4主机将传输类型更改为NONSEQ，并向地址0x10发起新的突发。T4-T6 HREADY LOW时，主机必须保持HTRANS恒定。T5-T6未定义长度突发以HREADY HIGH结束，并且主控器开始第一个节拍到地址0x10。T6-T7到地址0x10的INCR4传输的第一个节拍完成，主设备开始到地址0x14的下一个节拍。HADDR[31:0]0x64 HCLK 0x68 HBURST[2:0]INCR HREADY 0x10 0x14 HRDATA[31:0]INCR4 HTRANS[1:0]SEQ BUSY NONSEQ T0 T1 T2 T4 T5 T6 T7 INCR INCR4数据（0x64）数据（0x10）3传输3.6等待传输3-42版权所有ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.6.2等待状态期间的地址更改当从设备请求等待状态时，主设备只能更改地址一次，以下内容除外：•在IDLE传输期间。•在第3-43页出现错误响应后。在IDLE传输期间在等待传输期间，允许主机更改IDLE传输的地址。当HTRANS传输类型变为NONSEQ时，主机必须保持地址恒定，直到HREADY为HIGH。图3-16显示了等待的SINGLE突发传输，地址在IDLE传输期间发生变化。图3-16空闲状态下等待传输期间的地址变化
INCR8, and INCR16. • WRAP4, WRAP8, and WRAP16. Figure 3-14 shows a waited transfer in a fixed length burst, with a transfer type change from BUSY to SEQ. Figure 3-14 Waited transfer, BUSY to SEQ for a fixed length burst In Figure 3-14: T0-T1 The master initiates the next beat of the INCR4 burst to address 0x24. T1-T3 The master inserts a BUSY transfer to address 0x28. The slave inserts wait states with HREADYOUT = LOW. T3-T4 The master changes the transfer type to SEQ and initiates the next beat of the burst to address 0x28. T4-T6 With HREADY LOW, the master must keep HTRANS constant. T5-T6 Beat to address 0x24 completes with HREADY HIGH. T6-T7 Third beat of the INCR4 transfer to address 0x28 completes and the master starts the final beat to address 0x2C. HADDR[31:0] 0x24 HCLK 0x28 HBURST[2:0] INCR4 HREADY 0x28 0x2C HRDATA[31:0] INCR4 HTRANS[1:0] SEQ BUSY SEQ SEQ T0 T1 T2 T3 T4 T5 T6 T7 INCR4 INCR4 Data (0x24) Data (0x28) 3 Transfers 3.6 Waited transfers ARM IHI 0033B.b Copyright ARM Limited or its affiliates. All rights reserved. 3-41 ID102715 Non-Confidential BUSY transfer, undefined length burst During a waited transfer for an undefined length burst, INCR, the master is permitted to change from BUSY to any other transfer type, when HREADY is LOW. The burst continues if a SEQ transfer is performed but terminates if an IDLE or NONSEQ transfer is performed. Figure 3-15 shows a waited transfer during an undefined length burst, with a transfer type change from BUSY to NONSEQ. Figure 3-15 Waited transfer, BUSY to NONSEQ for an undefined length burst In Figure 3-15: T0-T1 The master initiates the next beat of the INCR burst to address 0x64. T1-T3 The master inserts a BUSY transfer to address 0x68. The slave inserts wait states with HREADYOUT = LOW. T3-T4 The master changes the transfer type to NONSEQ andinitiates a new burst to address 0x10. T4-T6 With HREADY LOW, the master must keep HTRANS constant. T5-T6 Undefined length burst completes with HREADY HIGH and the master starts the first beat to address 0x10. T6-T7 First beat of the INCR4 transfer to address 0x10 completes and the master starts the next beat to address 0x14. HADDR[31:0] 0x64 HCLK 0x68 HBURST[2:0] INCR HREADY 0x10 0x14 HRDATA[31:0] INCR4 HTRANS[1:0] SEQ BUSY NONSEQ SEQ T0 T1 T2 T3 T4 T5 T6 T7 INCR INCR4 Data (0x64) Data (0x10) 3 Transfers 3.6 Waited transfers 3-42 Copyright ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 3.6.2 Address changes during wait states When the slave is requesting wait states, the master can only change the address once, except as described in: • During an IDLE transfer. • After an ERROR response on page 3-43. During an IDLE transfer During a waited transfer, the master is permitted to change the address for IDLE transfers. When the HTRANS transfer type changes to NONSEQ the master must keep the address constant, until HREADY is HIGH. Figure 3-16 shows a waited transfer for a SINGLE burst, with the address changing during the IDLE transfers. Figure 3-16 Address changes during a waited transfer, with an IDLE
