IS200ISBEH2A DCS模块卡件,工业卡件
0b111 INCR16 16拍递增突发3传输3.5突发操作ARM IHI 0033B。b版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。3-35 ID102715非机密3.5.1 BUSY传输后的突发终止在突发开始后，如果在继续突发中的下一次传输之前需要更多时间，则主设备使用BUSY传输。在未定义长度的突发INCR期间，主机可能会插入BUSY传输，然后决定不再需要数据传输。在这些情况下，主机可以执行NONSEQ或IDLE传输，然后有效地终止未定义长度的突发。对于以下类型的固定长度脉冲串，该协议不允许主机通过BUSY传输结束脉冲串：•递增INCR4、INCR8和INCR16。•包装WRAP4、WRAP8和WRAP16。这些固定长度突发类型必须以序列转移终止。主设备不允许在单脉冲串后立即执行BUSY传输。SINGLE突发之后必须是IDLE传输或NONSEQ传输。3.5.2早期突发终止突发可以通过以下任一方式终止：•从错误响应。•多层互连终端。从站错误响应如果从站提供错误响应，则主站可以取消突发中的剩余传输。然而，这不是一个严格的要求，主设备也可以在突发中继续剩余的传输。如果主设备取消脉冲串中的剩余传输，则它必须在两个周期错误响应期间改变HTRANS以指示IDLE。如果主设备没有完成该突发，那么当它下次访问该从设备时，不需要它重建突发。例如，如果主设备只完成了八拍突发的三拍，那么在下次访问从属设备时，它不必完成剩余的五次传输。多层互连终止虽然主设备不允许提前终止突发请求，但如果突发未完成，从属设备必须设计为正常工作。当在多主系统中使用多层互连组件时，它可以终止突发，以便另一个主系统可以访问从系统。从属设备必须终止来自原始主设备的脉冲串，然后在发生这种情况时对新主设备做出适当响应。3转让3.5突发操作3-36版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.5.3突发示例各种突发示例如下所示：•四拍环绕突发，WRAP4。•四拍递增脉冲串，INCR4，第3-37页。•八拍包装爆裂，WRAP8，第3-37页。•八拍递增脉冲串，INCR8，第3-38页。•未定义长度突发，INCR第3-38页。四拍环绕脉冲串，WRAP4图3-8显示了使用四拍环绕突发的写入传输，并为第一次传输添加了等待状态。图3-8四拍环绕脉冲串由于脉冲串是字传输的四拍脉冲串，所以地址在16字节边界处环绕，向地址0x3C的传输之后是向地址0x30的传输。HADDR[31:0]0x38 HCLK 0x34 HWRITE HBURST[2:0]WRAP4 HREADY 0x3C HWDATA[31:0]数据（0x30）数据（0x38）T3 HTRANS[1:0]NONSEQ SEQ 0x30数据（0x34）HSIZE[2:0]Word HPROT[3:0]T0 T1 T2 T4 T5 T6 3传输3.5突发操作ARM IHI 0033B。b版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。3-37 ID102715非机密四拍递增突发，INCR4图3-9显示了使用四拍递增脉冲串的读取传输，并为第一次传输添加了等待状态。在这种情况下，地址不在16字节边界处换行，地址0x3C之后是到地址0x40的传输。图3-9四拍递增脉冲串八拍环绕脉冲串，WRAP8图3-10显示了使用八拍环绕突发的读取传输。图3-10八拍包装爆裂因为爆裂是八拍
0b111 INCR16 16-beat incrementing burst 3 Transfers 3.5 Burst operation ARM IHI 0033B.b Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. 3-35 ID102715 Non-Confidential 3.5.1 Burst termination after a BUSY transfer After a burst has started, the master uses BUSY transfers if it requires more time before continuing with the next transfer in the burst. During an undefined length burst, INCR, the master might insert BUSY transfers and then decide that no more data transfers are required. Under these circumstances, it is acceptable for the master to then perform a NONSEQ or IDLE transfer that then effectively terminates the undefined length burst. The protocol does not permit a master to end a burst with a BUSY transfer for fixed length bursts of type: • Incrementing INCR4, INCR8, and INCR16. • Wrapping WRAP4, WRAP8, and WRAP16. These fixed length burst types must terminate with a SEQ transfer. The master is not permitted to perform a BUSY transfer immediately after a SINGLE burst. SINGLE bursts must be followed by an IDLE transfer or a NONSEQ transfer. 3.5.2 Early burst termination Bursts can be terminated by either: • Slave error response. • Multi-layer interconnect termination. Slave error response If a slave provides an ERROR response then the master can cancel the remaining transfers in the burst. However, this is not a strict requirement and it is also acceptable for the master to continue the remaining transfers in the burst. If the master cancels the remaining transfers in the burst then it must change HTRANS to indicate IDLE during the two-cycle Error response. If the master does not complete that burst then there is no requirement for it to rebuild the burst when it next accesses that slave. For example, if a master only completes three beats of an eight-beat burst then it does not have to complete the remaining five transfers when it next accesses that slave. Multi-layer interconnect termination Although masters are not permitted to terminate a burst request early, slaves must be designed to work correctly if the burst is not completed. When a multi-layer interconnect component is used in a multi-master system then it can terminate a burst so that another master can gain access to the slave. The slave must terminate the burst from the original master and then respond appropriately to the new master if this occurs. 3 Transfers 3.5 Burst operation 3-36 Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 3.5.3 Burst examples Examples of various bursts are shown in the following sections: • Four-beat wrapping burst, WRAP4. • Four-beat incrementing burst, INCR4 on page 3-37. • Eight-beat wrapping burst, WRAP8 on page 3-37. • Eight-beat incrementing burst, INCR8 on page 3-38. • Undefined length bursts, INCR on page 3-38. Four-beat wrapping burst, WRAP4 Figure 3-8 shows a write transfer using a four-beat wrapping burst, with a wait state added for the first transfer. Figure 3-8 Four-beat wrapping burst Because the burst is a four-beat burst of word transfers, the address wraps at 16-byte boundaries, and the transfer to address 0x3C is followed by a transfer to address 0x30. HADDR[31:0] 0x38 HCLK 0x34 HWRITE HBURST[2:0] WRAP4 HREADY 0x3C HWDATA[31:0] Data (0x30) Data (0x38) T3 HTRANS[1:0] NONSEQ SEQ SEQ SEQ 0x30 Data (0x3C) Data (0x34) HSIZE[2:0] Word HPROT[3:0] T0 T1 T2 T4 T5 T6 3 Transfers 3.5 Burst operation ARM IHI 0033B.b Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. 3-37 ID102715 Non-Confidential Four-beat incrementing burst, INCR4 Figure 3-9 shows a read transfer using a four-beat incrementing burst, with a wait state added for the first transfer. In this case, the address does not wrap at a 16-byte boundary and the address 0x3C is followed by a transfer to address 0x40. Figure 3-9 Four-beat incrementing burst Eight-beat wrapping burst, WRAP8 Figure 3-10 shows a read transfer using an eight-beat wrapping burst. Figure 3-10 Eight-beat wrapping burst Because the burst is an eight-beat
