IS200ITBAG1A处理器卡件
3-29 ID102715非机密图3-3显示了具有两个等待状态的读取传输。图3-3具有两个等待状态的读传输图3-4显示了具有一个等待状态下的写传输。图3-4具有一个等待状态的写入传输注意：对于写入操作，主机在整个扩展周期内保持数据稳定。对于读取传输，在传输即将完成之前，从设备不必提供有效数据。有关使用稳定数据的更多信息，请参阅第7-68页的时钟。当以这种方式扩展传输时，它具有扩展下一个传输的地址阶段的副作用。图3-5显示了向不相关地址A、B和C的三次传输，地址C具有扩展的地址阶段。图3-5中的多次传输：•向地址A和C的传输为零等待状态•向地址B的传输为一等待状态•将向地址B传输的数据阶段扩展具有将向地址C传输的地址阶段扩展的效果。HADDR[31:0]A HCLK B地址阶段数据阶段HWRITE HRDATA[31:0]数据（A）HREADY HADDR[31:0]A HCLKA地址阶段数据相位HWRITE HWDATA[31:0]数据（B）HREADD HADDR[31:00]A HCLK B HWRITE写入（A）HRADATA[31:0]（B）HRADY读取（B）C HWDATA[31:00]数据（C）写入（C）T0 T1 T2 T4 T5 3传输3.2传输类型3-30版权所有©2001，2006，2010，2015 ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.2传输类型传输可分为四种类型之一，由HTRANS[1:0]控制。表3-1列出了这些。表3-1传输类型编码HTRANS[1:0]类型描述0b00 IDLE表示不需要数据传输。当主机不想执行数据传输时，它使用IDLE传输。建议主机使用IDLE传输终止锁定传输。从属设备必须始终为IDLE传输提供零等待状态OKAY响应，并且从属设备必须忽略该传输。0b01 BUSY BUSY传输类型允许主机在突发期间插入空闲周期。此传输类型表示主设备正在继续进行突发传输，但下一次传输不能立即进行。当主设备使用BUSY传输类型时，地址和控制信号必须反映脉冲串中的下一次传输。只有未定义长度的突发可以作为突发的最后一个周期进行BUSY传输。参见第3-35页的BUSY传输后的突发终止。从属设备必须始终为BUSY传输提供零等待状态OKAY响应，并且从属设备必须忽略该传输。0b10 NONSEQ表示单次传输或突发的第一次传输。地址和控制信号与先前的传输无关。总线上的单个传输被视为长度为1的突发，因此传输类型为非顺序传输。0b11 SEQ突发中的剩余传输是顺序的，并且地址与先前的传输相关。控制信息与先前的传输相同。地址等于上一次传输的地址加上传输大小（以字节为单位），传输大小由HSIZE[2:0]信号发出信号。在环绕突发的情况下，传输的地址在地址边界处环绕。3转让3.2转让类型ARM IHI 0033B。b版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。3-31 ID102715非机密图3-6显示了NONSEQ、BUSY和SEQ传输类型的使用。图3-6传输类型示例图3-6：T0-T1 4位读取以NONSEQ传输开始。T1-T2主机无法执行第二拍，并插入BUSY传输以延迟第二拍的开始。从设备为第一拍提供读取数据。T2-T3主设备现在准备好开始第二个节拍，因此发出序列转移信号。主设备忽略从设备在读数据总线上提供的任何数据。T3-T4大师进行第三拍。从设备为第二节拍提供读取数据。T4-T5大师演奏最后一拍。从属设备无法完成传输，并使用HREADYOUT插入单个等待状态。T5-T6从设备为第三拍提供读取数据。T6-T7从设备为最后一个节拍提供读取数据。HADDR[31:0]0x20 HCLK 0x24 HWRITE HBURST[2:0]INCR HREADY 0x2C HRDATA[31:0]数据（0x20）数据（0x28）HTRANS[1:0]NONSEQ BUSY ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 3.3锁定传输如果主机需要
3-29 ID102715 Non-Confidential Figure 3-3 shows a read transfer with two wait states. Figure 3-3 Read transfer with two wait states Figure 3-4 shows a write transfer with one wait state. Figure 3-4 Write transfer with one wait state Note For write operations the master holds the data stable throughout the extended cycles. For read transfers the slave does not have to provide valid data until the transfer is about to complete. For further information on the use of stable data, see Clock on page 7-68. When a transfer is extended in this way it has the side-effect of extending the address phase of the next transfer. Figure 3-5 shows three transfers to unrelated addresses, A, B, and C with an extended address phase for address C. Figure 3-5 Multiple transfers In Figure 3-5: • the transfers to addresses A and C are zero wait state • the transfer to address B is one wait state • extending the data phase of the transfer to address B has the effect of extending the address phase of the transfer to address C. HADDR[31:0] A HCLK B Address phase Data phase HWRITE HRDATA[31:0] Data (A) HREADY HADDR[31:0] A HCLK B Address phase Data phase HWRITE HWDATA[31:0] Data (A) HREADY HADDR[31:0] A HCLK B HWRITE Write (A) HRDATA[31:0] Data (B) HREADY Read (B) C HWDATA[31:0] Data (A) Write (C) Data (C) T0 T1 T2 T3 T4 T5 3 Transfers 3.2 Transfer types 3-30 Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 3.2 Transfer types Transfers can be classified into one of four types, as controlled by HTRANS[1:0]. Table 3-1 lists these. Table 3-1 Transfer type encoding HTRANS[1:0] Type Description 0b00 IDLE Indicates that no data transfer is required. A master uses an IDLE transfer when it does not want to perform a data transfer. It is recommended that the master terminates a locked transfer with an IDLE transfer. Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer must be ignored by the slave. 0b01 BUSY The BUSY transfer type enables masters to insert idle cycles in the middle of a burst. This transfer type indicates that the master is continuing with a burst but the next transfer cannot take place immediately. When a master uses the BUSY transfer type the address and control signals must reflect the next transfer in the burst. Only undefined length bursts can have a BUSY transfer as the last cycle of a burst. See Burst termination after a BUSY transfer on page 3-35. Slaves must always provide a zero wait state OKAY response to BUSY transfers and the transfer must be ignored by the slave. 0b10 NONSEQ Indicates a single transfer or the first transfer of a burst. The address and control signals are unrelated to the previous transfer. Single transfers on the bus are treated as bursts of length one and therefore the transfer type is NONSEQUENTIAL. 0b11 SEQ The remaining transfers in a burst are SEQUENTIAL and the address is related to the previous transfer. The control information is identical to the previous transfer. The address is equal to the address of the previous transfer plus the transfer size, in bytes, with the transfer size being signaled by the HSIZE[2:0] signals. In the case of a wrapping burst the address of the transfer wraps at the address boundary. 3 Transfers 3.2 Transfer types ARM IHI 0033B.b Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. 3-31 ID102715 Non-Confidential Figure 3-6 shows the use of the NONSEQ, BUSY, and SEQ transfer types. Figure 3-6 Transfer type examples In Figure 3-6: T0-T1 The 4-beat read starts with a NONSEQ transfer. T1-T2 The master is unable to perform the second beat and inserts a BUSY transfer to delay the start of the second beat. The slave provides the read data for the first beat. T2-T3 The master is now ready to start the second beat, so a SEQ transfer is signaled. The master ignores any data that the slave provides on the read data bus. T3-T4 The master performs the third beat. The slave provides the read data for the second beat. T4-T5 The master performs the last beat. The slave is unable to complete the transfer and uses HREADYOUT to insert a single wait state. T5-T6 The slave provides the read data for the third beat. T6-T7 The slave provides the read data for the last beat. HADDR[31:0] 0x20 HCLK 0x24 HWRITE HBURST[2:0] INCR HREADY 0x2C HRDATA[31:0] Data (0x20) Data (0x28) HTRANS[1:0] NONSEQ BUSY ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 3.3 Locked transfers If the master requires
