IS200IVSHG1ABB通用电气卡件
有限公司或其附属公司。保留所有权利。1-17 ID102715非机密1.2 AHB版本本规范的前一版本称为A版，并描述了称为AHB Lite的版本。此版本的文档为B版，描述了：AHB Lite此版本与A版中定义的版本相同。AHB5此版本提供了其他功能，并使用属性声明新功能。如果未声明属性，则将其视为False。新属性为：•Extended_Memory_Types。请参阅第3-45页的内存类型。•安全传输。请参阅第3-50页的安全传输。•恩迪亚。参见第6-61页的Endianness。•Stable_Between_Clock。参见第7-68页的时钟。•排他性转移。见第8章独家转让。•Multi_Copy_Atomicity。参见第9-77页的多拷贝原子性。本规范修订版还包含以下主题的附加信息：•锁定传输。参见第3-32页的锁定传输。•多重从属选择。请参见第4-53页的多个从属选择。•单拷贝原子大小。参见第9-76页的单副本原子大小。•用户信令。参见第10章用户信令。在本规范中，术语AHB用于指代AHB Lite和AHB5。除非另有说明，信号对AHB Lite和AHB5都是通用的。1简介1.3操作1-18版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 1.3操作主机通过驱动地址和控制信号启动传输。这些信号提供有关传输的地址、方向和宽度的信息，并指示传输是否构成突发的一部分。转账可以是：•单人转账。•不在地址边界换行的递增脉冲串。•在特定地址边界处换行的换行脉冲串。写数据总线将数据从主设备移动到从设备，而读数据总线将从设备移动到主设备。每个传输包括：地址阶段一个地址和控制周期。数据阶段数据的一个或多个周期。从属设备不能请求扩展地址阶段，因此所有从属设备必须能够在此期间对地址进行采样。然而，从设备可以请求主设备使用HREADY扩展数据阶段。当低电平时，该信号使等待状态被插入到传输中，并使从设备有额外的时间来提供或采样数据。从属设备使用HRESP指示传输的成功或失败。ARM IHI 0033B.b版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。2-19 ID102715非保密第2章信号描述本章描述协议信号。它包含以下部分：•第2-20页上的全局信号。•主信号见第2-21页。•第2-23页上的从属信号。•解码器信号见第2-24页。•多路复用器信号见第2-25页。注：所有AHB Lite和AHB5信号都以字母H作为前缀，以区别于系统设计中其他类似命名的信号。2信号说明2.1全球信号2-20版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。ARM IHI 0033B.b非机密ID102715 2.1全局信号表2-1列出了协议全局信号。表2-1全局信号名称源描述HCLK时钟源总线时钟计时所有总线传输。所有信号定时都与HCLK的上升沿有关。参见第7-68页的时钟。HRESETn重置控制器总线重置信号激活为LOW，重置系统和总线。这是唯一激活的LOW信号。参见第7-68页的重置。2信号说明2.2主信号ARM IHI 0033B。b版权所有©2001、2006、2010、2015 ARM Limited或其附属公司。保留所有权利。2-21 ID102715非机密2.2主信号表2-2列出了由主设备生成的协议信号。表2-2主信号名称目标描述HADDR[31:0]从和解码器32位系统地址总线。HBURST[2:0]从脉冲串类型指示传输是单次传输还是形成脉冲串的一部分。支持4、8和16拍的固定长度突发。突发可以是递增或换行。还支持未定义长度的递增突发。参见第3-34页的突发操作。HMASTLOCK Slave（高）时，表示电流传输是锁定序列的一部分。它具有与地址和控制信号相同的定时。请参阅锁定的传输
Limited or its affiliates. All rights reserved. 1-17 ID102715 Non-Confidential 1.2 AHB revisions The previous issue of this specification is referred to as Issue A and describes the version that is called AHB-Lite. This issue of the document is Issue B and describes: AHB-Lite This version is the same as defined in Issue A. AHB5 This version provides additional capabilities, and a property is used to declare a new capability. If a property is not declared, it is considered False. The new properties are: • Extended_Memory_Types. See Memory types on page 3-45. • Secure_Transfers. See Secure transfers on page 3-50. • Endian. See Endianness on page 6-61. • Stable_Between_Clock. See Clock on page 7-68. • Exclusive_Transfers. See Chapter 8 Exclusive Transfers. • Multi_Copy_Atomicity. See Multi-copy atomicity on page 9-77. This revision of the specification also contains additional information on the following topics: • Locked transfers. See Locked transfers on page 3-32. • Multiple slave select. See Multiple slave select on page 4-53. • Single-copy atomicity size. See Single-copy atomicity size on page 9-76. • User signaling. See Chapter 10 User Signaling. In this specification, the term AHB is used to refer to both AHB-Lite and AHB5. Unless stated, signals are common to both AHB-Lite and AHB5. 1 Introduction 1.3 Operation 1-18 Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 1.3 Operation The master starts a transfer by driving the address and control signals. These signals provide information about the address, direction, width of the transfer, and indicate if the transfer forms part of a burst. Transfers can be: • Single. • Incrementing bursts that do not wrap at address boundaries. • Wrapping bursts that wrap at particular address boundaries. The write data bus moves data from the master to a slave, and the read data bus moves data from a slave to the master. Every transfer consists of: Address phase One address and control cycle. Data phase One or more cycles for the data. A slave cannot request that the address phase is extended and therefore all slaves must be capable of sampling the address during this time. However, a slave can request that the master extends the data phase by using HREADY. This signal, when LOW, causes wait states to be inserted into the transfer and enables the slave to have extra time to provide or sample data. The slave uses HRESP to indicate the success or failure of a transfer. ARM IHI 0033B.b Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. 2-19 ID102715 Non-Confidential Chapter 2 Signal Descriptions This chapter describes the protocol signals. It contains the following sections: • Global signals on page 2-20. • Master signals on page 2-21. • Slave signals on page 2-23. • Decoder signals on page 2-24. • Multiplexor signals on page 2-25. Note All AHB-Lite and AHB5 signals are prefixed with the letter H to differentiate them from other similarly named signals in a system design. 2 Signal Descriptions 2.1 Global signals 2-20 Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. ARM IHI 0033B.b Non-Confidential ID102715 2.1 Global signals Table 2-1 lists the protocol global signals. Table 2-1 Global signals Name Source Description HCLK Clock source The bus clock times all bus transfers. All signal timings are related to the rising edge of HCLK. See Clock on page 7-68. HRESETn Reset controller The bus reset signal is active LOW and resets the system and the bus. This is the only active LOW signal. See Reset on page 7-68. 2 Signal Descriptions 2.2 Master signals ARM IHI 0033B.b Copyright © 2001, 2006, 2010, 2015 ARM Limited or its affiliates. All rights reserved. 2-21 ID102715 Non-Confidential 2.2 Master signals Table 2-2 lists the protocol signals generated by a master. Table 2-2 Master signals Name Destination Description HADDR[31:0] Slave and decoder The 32-bit system address bus. HBURST[2:0] Slave The burst type indicates if the transfer is a single transfer or forms part of a burst. Fixed length bursts of 4, 8, and 16 beats are supported. The burst can be incrementing or wrapping. Incrementing bursts of undefined length are also supported. See Burst operation on page 3-34. HMASTLOCK Slave When HIGH, indicates that the current transfer is part of a locked sequence. It has the same timing as the address and control signals. See Locked transfers on
