PM861 3BSE018129R1机器人模块卡件
UDFN8引脚编号类型描述VDD_IO 3 2电源+1.8V至+5V I/O信号电源输入引脚。VDD_IO电源电压不应大于VIN电压。VO_33 8 4功率+3.3V输出功率，来自集成LDO稳压器。对于自供电设计，向该引脚提供+3.3V。GND 1 7电源接地VIN 7 8电源USB端口VBUS输入电源。对于自供电设计，向该引脚提供+3.3V。产品数据表PL2303GL版本：2018年12月6日-13/23-版本0.8 8。功能描述本节详细介绍了PL2303GL的功能框图描述。8.1 USB 1.1 FS收发器USB收发器提供USB全速电信号要求和USB物理接口（DP/DM）。该模块还包括一个用于PLL的精密内部振荡器。PLL向其他逻辑功能提供时钟。该模块还包括USB数据线上的内部USB串联终端电阻器和DP信号的上拉电阻器。8.2 LDO稳压器此模块是5V至3.3V LDO稳压器，用于为USB收发器供电和驱动。它还包括3.3V断电检测输出信号，数字电路将使用该信号来重置芯片。LDO 5V至3.3V可为芯片内部和外部组件提供100mA的电源。8.3时钟发生器时钟发生器模块为内部芯片逻辑生成48MHz和12MHz参考时钟信号。处于挂起状态时，内部时钟将停止。8.4 USB FS SIE USB全速串行接口引擎（SIE）块执行USB DP/DM信号的处理。它将内部并行数据转换为串行数据，并输出到USB FS收发器以生成外部USB DP/DM信号定时。它还将通过USB FS收发器的外部USB DP/DM信号转换为内部电路的并行数据。此块支持USB数据包解码和编码。它还生成并检查分组CRC、比特填充、SYNC和EOP帧信号。DPLL模块将使用内部48MHz时钟同步外部DP/DM转换，为USB接口相关电路生成12MHz时钟。8.5电源管理该模块将监控USB连接和DP/DM信号状态，以创建重置状态、运行状态、挂起状态、唤醒状态等。重置和挂起信号由该模块生成。8.6控制端点控制端点模块处理控制端点数据包传输协议，如SETUP数据包、DATA数据包和返回状态数据包。产品数据表PL2303GL版本：2018年12月6日-14月23日-版本0.8 8.7批量输出端点批量输出端点模块处理批量输出端点数据包传输协议，如Data数据包和返回状态数据包。它还将USB主机批量输出数据传输到芯片出站FIFO。
UDFN8 Pin No. Type Description VDD_IO 3 2 Power +1.8V to +5V I/O signal power input pin. VDD_IO supply voltage should not be larger than VIN voltage. VO_33 8 4 Power +3.3V output power from integrated LDO regulator. For self-powered design, supply +3.3V to this pin. GND 1 7 Power Ground VIN 7 8 Power USB port VBUS input power supply. For self-powered design, supply +3.3V to this pin. Product Data Sheet PL2303GL Release: Dec. 6, 18 - 13 / 23 - Rev.0.8 8. Functional Description This section details the functional block diagram description of the PL2303GL. 8.1 USB 1.1 FS Transceiver The USB Transceiver provides the USB full-speed electrical signal requirements and USB physical interface (DP/DM). This block also includes one precise internal oscillator for PLL. The PLL provides the clock to other logic functions. This block also includes the internal USB series termination resistors on the USB data lines and pull-up resistor for the DP signal. 8.2 LDO Regulator This block is the 5V to 3.3V LDO regulator to power and drive the USB transceiver. It also includes 3.3V brownout detection output signals that will be used by digital circuit to reset the chip. The LDO 5V to 3.3V can supply 100mA for chip internal and external components. 8.3 Clock Generator The clock generator module generates the 48MHz and 12MHz reference clock signals for internal chip logic. The internal clocks will be stopped while in suspend state. 8.4 USB FS SIE The USB Full-Speed Serial Interface Engine (SIE) block performs the processing of USB DP/DM signals. It translates the internal parallel data to serial data and outputs to USB FS transceiver to generate external USB DP/DM signals timing. It also translates external USB DP/DM signals pass through USB FS transceiver to parallel data for internal circuit. This block supports USB packet decoding and encoding. It also generates and check packet CRC, bit stuffing, SYNC and EOP frame signal. The DPLL module will use the internal 48MHz clock to synchronize external DP/DM transitions to generate 12MHz clock for USB interface related circuit. 8.5 Power Management This module will monitor the USB attachment and DP/DM signals state to create reset state, running state, suspend state, wakeup state, etc. Reset and suspend signals are generated from this module. 8.6 Control Endpoint The Control Endpoint module handles control endpoint packet transfer protocols such as SETUP packet, DATA packet and return status packet. Product Data Sheet PL2303GL Release: Dec. 6, 18 - 14 / 23 - Rev.0.8 8.7 Bulk Out Endpoint The Bulk Out Endpoint module handles bulk-out endpoint packet transfer protocols such as DATA packet and return status packet. It also transfers USB host bulk-out data to chip outbound FIFO.
