3BHE035301R1002机器人模块
定时器
通过在相应的“timer x Enable”（定时器x启用）字段中写入“1”，可以独立启用每个定时器。类似地，通过将“1”写入适当的“timer x IRQ Enable”（定时器x IRQ启用）字段，可以独立启用每个定时器产生的中断。如果定时器产生了中断，可以通过读取“定时器x引起的IRQ”字段来确定中断的来源。如果该字段设置为“1”，则相应的计时器导致中断。请注意，多个计时器可能会导致单个中断。因此，必须读取所有计时器的状态，以确保识别所有中断源。通过将“0”写入相应的“timer x Caused IRQ”字段，可以清除特定的定时器中断。或者，写入适当的Timer x IRQ Clear（TxIC）寄存器也将清除中断。使用“Timer x Caused IRQ”（定时器x引起的IRQ）字段清除中断时，请注意，确保使用正确的位掩码非常重要，这样其他寄存器设置就不会受到影响。清除中断的首选方法是使用第52页所述的“定时器x IRQ清除”寄存器。定时器控制状态寄存器2（TCSR2）定时器也由定时器控制状态计数器2（TCSR2）中的位控制，该位位于BAR2地址的偏移量0x04处。该寄存器中的位映射如下：“读取锁存选择”位用于选择可编程定时器的锁存模式。如果该位设置为“0”，则每个定时器输出在读取其任何一个地址时被锁存。
例如，
对TMRCCR12寄存器的读取锁存定时器1和2的计数。对TMRCCR 3寄存器的读取则锁存定时器3的计数。每次对这些寄存器中的任何一个进行读取时，都会继续这样。因此，不可能时钟速率MSb LSb 2MHz 0 0 1MHz 0 1 500kHz 1 0 250kHz 1 1字段位读取或写入读取锁存器选择TCSR2[0]R/W Reserved All Other Bits R/W所有这些位在系统复位后默认为“0”。50 3 VMIVME-7807/VME-7807RC产品手册记录了给定时间内所有四个定时器的值。然而，通过将该位设置为“1”，所有四个计时器输出将仅在读取计时器1和2当前计数寄存器（TMRCCR12）时被锁存。因此，要同时捕获所有四个计时器的当前计数，首先读取TMRCCR12（32位读取），然后读取TMRCCR 3和TMRCCR4。第一次读取（读取TMRCCR12寄存器）会导致所有四个定时器值同时锁存。随后对TMRCCR3和TMRCCR4寄存器的读取不会锁存新的计数值，从而可以获得同一时刻的所有计时器的计数。定时器1和2加载计数寄存器（TMRLCR12）定时器1和定时器2为16位宽，从位于偏移量0x的定时器1和2中加载计数寄存器中获取其加载计数
Timer
Each timer can be enabled independently by writing "1" in the corresponding "timer x Enable" field. Similarly, by writing "1" to the appropriate "timer x IRQ Enable" field, the interrupts generated by each timer can be enabled independently. If the timer generates an interrupt, you can determine the source of the interrupt by reading the "IRQ Caused by Timer x" field. If this field is set to "1", the corresponding timer causes an interrupt. Note that multiple timers can cause a single interrupt. Therefore, the status of all timers must be read to ensure that all interrupt sources are identified. Specific timer interrupts can be cleared by writing "0" to the corresponding "timer x Caused IRQ" field. Alternatively, writing the appropriate Timer x IRQ Clear (TxIC) register will also clear the interrupt. When using the "Timer x Caused IRQ" field to clear interrupts, note that it is important to ensure that the correct bit mask is used so that other register settings are not affected. The preferred method for clearing interrupts is to use the Timer x IRQ Clear register described on page 52. The timer control status register 2 (TCSR2) is also controlled by the bit in the timer control status counter 2 (TCSR2), which is located at the offset 0x04 of the BAR2 address. The bit mapping in this register is as follows: The "Read Latch Select" bit is used to select the latch mode of the programmable timer. If this bit is set to "0", each timer output is latched when reading any of its addresses.
For example,
Count the read latch timers 1 and 2 of the TMRCCR12 register. Reading the TMRCCR 3 register locks the count of timer 3. This continues each time any of these registers is read. Therefore, it is impossible for the clock rate MSb LSb 2MHz 0 0 1MHz 0 1 500kHz 1 0 250kHz 1 1 field bit to read or write to the read latch. Select TCSR2 [0] R/W Reserved All Other Bits R/W All these bits are "0" by default after the system is reset. 50 3 VMIVME-7807/VME-7807RC product manual records the values of all four timers in a given time. However, by setting this bit to "1", all four timer outputs will be latched only when the timer 1 and 2 current count registers (TMRCCR12) are read. Therefore, to capture the current counts of all four timers simultaneously, read TMRCCR12 (32-bit read) first, then TMRCCR 3 and TMRCCR4. The first read (reading TMRCCR12 register) will cause all four timer values to latch at the same time. The subsequent reading of TMRCCR3 and TMRCCR4 registers will not latch the new count value, so that the count of all timers at the same time can be obtained. Timer 1 and 2 load count registers (TMRLCR12) Timer 1 and timer 2 are 16 bit wide, and their load counts are obtained from the load count registers of timer 1 and 2 at offset 0xTimer
