150-C85NBD自动化模块备件
如果CPU执行输出扫描一段时间后停止
则在刷新周期到期后，FBC的输出数据将变为未刷新。（请参阅网络配置FBC参数刷新系数和刷新偏移。如果CPU在输出扫描之间必须有很长的时间，可能需要调整刷新参数以避免网络上有未刷新的数据。）配置异步I/O扫描在PLC CPU中，默认情况下，所有时隙都分配给固定扫描集#1。扫描集#1是一个异步扫描集，其周期等于扫描周期，没有输出延迟。作为该扫描集的一部分，在逻辑执行之前扫描输入，并且在逻辑执行之后立即扫描输出。可以定义多达32个异步扫描集，每个扫描集具有不同的周期和输出延迟。可以将任何数量的时隙分配给单个扫描集。但给定的时隙可以仅分配给一个扫描集。PLC CPU中的扫描集具有90–70系列系统手册（GFK–1192）中定义的各种可配置参数。4 4-6系列90-70 FIP总线控制器用户手册–1997年11月GFK-1038A同步I/O扫描如果需要定期处理一组连贯的输入数据，则需要同步I/O扫描。可以为FIP总线控制器定义多达15个同步扫描集。在同步I/O扫描模式下，在FIP总线控制器完成同步扫描集中所有输入数据和验证程序的消耗后，PLC CPU执行同步应用程序。FIP总线控制器触发PLC CPU，CPU调度指定的应用程序。PLC CPU将扫描集输入扫描到PLC参考表中，程序启动。
逻辑结束时
PLC CPU执行输出扫描（如果已配置）。为了正常运行，程序应在FIP总线控制器被安排产生网络输出之前完成逻辑并执行输出扫描。有关定时的更多详细信息，请参阅重要产品信息文档GFK-1200。下图显示了典型同步应用程序的定时特性。在此示例中，单个同步扫描集被配置为包含时隙DI和DO。FBC Cons Delay FBC ConsCPU Input Delay CPU Input Scan CPU Logic CPU Output Scan FBC Prod Delay DI DO FBC ProdDI DO时隙DI和DO DI离散输入传输时隙的周期：定义的传输时隙，包含同步扫描集的输入数据。为了允许PLC应用程序的最大时间，输入时隙配置在比输出时隙早但与输出时隙相邻的相位。DO离散输出传输时隙：定义的传输时隙，包含同步扫描集的输出数据。为了允许PLC应用程序的最大时间，输出时隙配置在比输入时隙晚但与输入时隙相邻的相位。FBC Cons Delay FBC Consument Delay：在调度输入TVA的消耗之前，FBC中的固定延迟。此时间固定为1ms。
If the CPU stops after performing an output scan for a period of time
After the refresh cycle expires, the output data of FBC will not be refreshed. (See Network Configuration FBC Parameters Refresh Factor and Refresh Offset. If the CPU must have a long time between output scans, you may need to adjust the refresh parameters to avoid data not refreshed on the network.) Configure asynchronous I/O scanning in the PLC CPU. By default, all time slots are allocated to fixed scan set # 1. Scan set # 1 is an asynchronous scan set with a cycle equal to the scan cycle and no output delay. As part of the scan set, the input is scanned before logical execution and the output is scanned immediately after logical execution. Up to 32 asynchronous scan sets can be defined, each with a different cycle and output delay. Any number of time slots can be allocated to a single scan set. However, a given time slot can be allocated to only one scan set. The scan set in the PLC CPU has various configurable parameters defined in the Series 90 – 70 System Manual (GFK – 1192). 4 4-6 Series 90-70 FIP Bus Controller User's Manual – November 1997 GFK-1038A Synchronous I/O Scan If a set of consistent input data needs to be processed regularly, synchronous I/O scanning is required. Up to 15 synchronous scan sets can be defined for the FIP Bus Controller. In synchronous I/O scan mode, after FIP bus controller finishes consuming all input data and verification programs in synchronous scan set, PLC CPU executes synchronous application program. The FIP bus controller triggers the PLC CPU, and the CPU dispatches the specified application program. The PLC CPU scans the scan set input into the PLC reference table, and the program starts.
At the end of logic
The PLC CPU performs an output scan (if configured). For normal operation, the program shall complete logic and perform output scanning before FIP Bus Controller is scheduled to generate network output. For more details on timing, refer to the important product information document GFK-1200. The following figure shows the timing characteristics of a typical synchronous application. In this example, a single synchronous scan set is configured to include timeslots DI and DO. FBC Cons Delay FBC ConsCPU Input Delay CPU Input Scan CPU Logic CPU Output Scan FBC Prod Delay DI DO FBC ProdDI DO timeslot DI and DO DI Discrete Input Transmission timeslot cycle: defined transmission timeslot, including the Input data of synchronous Scan set. To allow the maximum time for the PLC application, the input timeslot is configured in a phase earlier than the output timeslot but adjacent to the output timeslot. DO Discrete Output Transmission Slot: the defined transmission slot, which contains the output data of the synchronous scan set. To allow the maximum time for the PLC application, the output timeslot is configured in a phase that is later than the input timeslot but adjacent to the input timeslot. FBC Cons Delay FBC Consumption Delay: The fixed delay in the FBC before the consumption of the input TVA is scheduled. This time is fixed at 1ms.
