26390582-CR DSTK132 工控模块卡件
锁存同步丢失
–当该位为高（1）时，接收器电路与输入信号失去同步一次或多次。该位被锁存。一旦设置，必须通过将零写入该位位置来清除。锁存同步丢失的断言通常表明接收器链路被有意或无意地断开，并且数据可能已经丢失。如果绑定到接收器的上游节点断电或被禁用，也会发生此事件。RX FIFO已满–当该位为高（1）时，RX FIFI已满一次或多次。该位被锁存。一旦设置，必须通过将零写入该位位置来清除。这是一种故障情况，数据可能已丢失。第09位：RX FIFO几乎满–当该位为高（1）时，RX FIFI几乎满了一次或多次。该位被锁存。一旦设置，必须通过将零写入该位位置来清除。RX FIFO几乎满位的断言表明接收器电路在最大容量下工作，在正常工作条件下，该事件不应发生。如果发生这种情况，PCI总线主控器应暂时暂停对板的所有写入和读取操作。
坏数据–当该位为高
（1）时，接收器电路检测到无效数据一次或多次。该位被锁存。一旦设置，必须通过将零写入该位位置来清除。位07：待定初始化。中断–当该位为高（1）时，电路板检测到来自网络上其他节点的一个或多个初始化中断。要查看哪些节点发送了初始化中断，请读取偏移量$3C处的初始化节点ID（INITN）FIFO。位06：流氓数据包故障-当该位设置为高（1）时，电路板作为流氓主机1或0运行，并检测并删除了流氓包。该位被锁存。一旦设置，必须通过将零（0）写入该位位置来清除。Artisan Technology Group-优质仪器…保证|（888）88-SOURCE | 5超高速光纤反射存储器，带中断本地中断状态寄存器位定义（结束）和04：保留-这些是保留的。位03：重置节点请求–当此位为高（1）时，网络上的另一个节点已请求本地PCI总线主控重置此板。 不会自动复位。
Loss of latch synchronization
– When this bit is high (1), the receiver circuit loses synchronization with the input signal one or more times. This bit is latched. Once set, it must be cleared by writing zero to this bit position. Assertions of latch synchronization loss usually indicate that the receiver link has been intentionally or unintentionally disconnected and that data may have been lost. This event also occurs if the upstream node bound to the receiver is powered down or disabled. RX FIFO Full – When this bit is high (1), RX FIFI is full one or more times. This bit is latched. Once set, it must be cleared by writing zero to this bit position. This is a fault condition and data may have been lost. Bit 09: RX FIFO is almost full – When this bit is high (1), RX FIFI is almost full once or more. This bit is latched. Once set, it must be cleared by writing zero to this bit position. The assertion that the RX FIFO is almost full indicates that the receiver circuit is operating at maximum capacity, and this event should not occur under normal operating conditions. If this happens, the PCI bus master controller should temporarily suspend all write and read operations to the board.
Bad data – when this bit is high
(1) When the receiver circuit detects invalid data one or more times. This bit is latched. Once set, it must be cleared by writing zero to this bit position. Bit 07: Pending initialization. Interrupt – When this bit is high (1), the board detects one or more initialization interrupts from other nodes on the network. To see which nodes have sent initialization interrupts, read the initialization node ID (INITN) FIFO at offset $3C. Bit 06: Rogue packet failure - When this bit is set to high (1), the circuit board runs as a rogue host 1 or 0, and the rogue packet is detected and deleted. This bit is latched. Once set, it must be cleared by writing zero (0) to this bit position. Artisan Technology Group - High quality instrument... Guarantee | (888) 88-SOURCE | 5 Ultra high speed optical fiber reflective memory, with interrupt local interrupt status register bit definition (end) and 04: Reserved - these are reserved. Bit 03: Reset Node Request – When this bit is high (1), another node on the network has requested the local PCI bus master to reset this board. It will not reset automatically.
