26390582-BM DSTK129工控模块卡件PLC
本地中断控制寄存器
（LISR和LIER包含许多PCI中断源。不是来自PLX PCI接口设备，而是来自本地板载设备的第二层中断称为LISR，如下面的表3-64所示，LIER如第78页的表3-65所示。所有本地中断在逻辑上“或”合并为PLX设备的单个中断输入。此输入称为LINTi#。LINTi#线又由PLX本地配置寄存器INTCSR的位11控制，偏移量为$68（至基址0）。本地中断的控制和状态在两个本地寄存器（LISR和LIER）中实现。这两个寄存器的位函数相互镜像。本地中断状态寄存器LISR包含一组中断状态标志，而LIER包含一组相应的启用。在任何本地中断都可能导致LINTi#中断之前，必须断言状态位、其启用和全局启用。
本地中断状态寄存器位定义
（续）全局中断启用–在LINTi#线被断言并可能导致PCI中断之前，除了LIER中的任何中断标志及其相关启用位外，该位必须设置为高（1）。如果LIER中的自动清除启用位设置为高（1），则在读取此寄存器（LISR）时，全局中断启用位将自动清除。该位可通过该寄存器进行读写访问，因此允许单个读修改写操作来服务本地中断。本地内存奇偶校验错误–当此位为高（1）时，在本地内存访问中检测到一个或多个奇偶校验。该位被锁存。一旦设置，必须通过将零写入该位位置来清除。注意，在奇偶校验有效之前，LCSR1的位27必须设置为高。还要注意，奇偶校验仅在L字和Q字访问上有效。禁止字和字节存储器写入访问。内存。禁止写入–当该位为高（1）时，当电路板处于奇偶校验启用模式时，尝试并禁止向本地存储器写入16位字或8位字节。该位被锁存。一旦设置，必须通过将零写入该位位置来清除。
Local interrupt control register
(LISR and LIER contain many PCI interrupt sources. Layer 2 interrupts not from PLX PCI interface devices, but from local onboard devices are called LISR, as shown in Table 3-64 below, and LIER is shown in Table 3-65 on page 78. All local interrupts are logically "OR" Merged into a single interrupt input of the PLX device. This input is called LINTi #. LINTi # line is controlled by bit 11 of PLX local configuration register INTCSR with an offset of $68 (to base address 0). The control and status of local interrupts are implemented in two local registers (LISR and LIER). The bit functions of these two registers mirror each other. The local interrupt status register LISR contains a set of interrupt status flags, while the LIER contains a corresponding set of enabled. Before any local interrupt can cause LINTi # interrupt, the status bit, its enable, and global enable must be asserted.
Local Interrupt Status Register Bit Definitions
(Continued) Global Interrupt Enable – This bit must be set high (1) in addition to any interrupt flag and its associated enable bit in the LIER before the LINTi# line is asserted and a PCI interrupt can result. If the Auto Clear enable bit in the LIER is set high (1), the Global Interrupt Enable bit will automatically be cleared as this register (LISR) is being read. This bit is read and write accessible with this register and thus allows a single read-modify-write operation to service the local interrupts. Local Memory Parity Error – When this bit is high (1), one or more parity errors have been detected on local memory accesses. This bit is latched. Once set, it must be cleared by writing a zero to this bit location. Note that Bit 27 of the LCSR1 must be set high before parity is active. Also note that parity works only on Lword and Qword accesses. Word and byte memory write access are inhibited. Mem. Write Inhibited – When this bit is high (1), a 16-bit word or an 8-bit byte write to local memory was attempted and inhibited while the board was in the parity enabled mode. This bit is latched. Once set, it must be cleared by writing a zero to this bit location.
