26390582-BL DSTK128 模块备件控制器
网络数据包
偏移1和偏移0–当主机PCI系统写入板载存储器并通过网络启动数据包时，偏移1和0将在通过网络发送或接收数据包时对网络地址应用偏移。偏移不会出现在对内存的本地访问上，并且当网络数据包通过板时，偏移不会改变它们。偏移量1和偏移量0提供四个可能的64兆字节的二进制增量，每个增量通过256兆字节的网络地址范围。当地址和偏移量超过256 MB网络地址范围时，超过256 M字节的地址位将被截断。这会导致写入循环到较低的内存位置。偏移1和0的位分别对应于网络地址位A27和A26 TX FIFO Empty–逻辑高（1）表示TX FIFI当前为空。该位仅提供即时状态（未锁存），为只读。TX FIFO几乎满–逻辑高（1）表示TX FIFI当前几乎满。该位仅提供即时状态（未锁存），为只读。此位的周期性断言是正常的。锁存RX FIFO满–逻辑高（1）表示RX FIFI至少经历过一次满状态。此位在此寄存器中为只读。要清除此情况，请写入本地中断状态寄存器中的相应位。
Network packets
Offsets 1 and 0 – When the host PCI system writes to on-board memory and starts packets over the network, offsets 1 and 0 apply offsets to network addresses when sending or receiving packets over the network. The offset does not appear on local access to memory, and when network packets pass through the board, the offset does not change them. Offset 1 and offset 0 provide four possible 64 megabyte binary increments, each passing through a 256 megabyte network address range. When the address and offset exceed the 256 MB network address range, the address bits exceeding 256 M bytes will be truncated. This causes the write to cycle to a lower memory location. The bits of offset 1 and 0 correspond to the network address bits A27 and A26 TX FIFO Empty – a logical high (1) indicates that TX FIFI is currently empty. This bit only provides instant status (not latched) and is read-only. TX FIFO almost full – A logic high (1) indicates that TX FIFI is almost full at present. This bit only provides instant status (not latched) and is read-only. Periodic assertion of this bit is normal. Latch RX FIFO Full – A logic high (1) indicates that RX FIFI has experienced a full state at least once. This bit is read-only in this register. To clear this condition, write the corresponding bit in the local interrupt status register.
锁存RX FIFO几乎满–逻辑高
（1）表示RX FIFI以最大可接受速率运行。在正常操作条件下，不应发生此事件。此位在此寄存器中为只读。要清除此情况，请写入本地中断状态寄存器中的相应位。锁存同步丢失–这是一个只读位。逻辑高（1）表示自上次清除标志以来，接收器电路至少检测到一次有效信号的丢失。在正常操作条件下，此事件不应发生，可能表示数据丢失。逻辑高可能指示接收器的链路被有意或无意地断开。RX Signal Detect（接收信号检测）–逻辑高（1）表示板接收器当前检测到光。该位仅提供即时状态（未锁存），为只读。
Latch RX FIFO almost full - logic high
(1) Indicates that RX FIFI is running at the maximum acceptable rate. This event should not occur under normal operating conditions. This bit is read-only in this register. To clear this condition, write the corresponding bit in the local interrupt status register. Latch synchronization lost – this is a read-only bit. A logic high (1) indicates that the receiver circuit has detected the loss of a valid signal at least once since the flag was last cleared. Under normal operating conditions, this event should not occur and may indicate data loss. A logic high may indicate that the receiver's link is intentionally or unintentionally disconnected. RX Signal Detect – logic high (1) indicates that the board receiver is currently detecting light. This bit only provides instant status (not latched) and is read-only.
