26390582-AY DSTK126工控模块卡件
DMA通道1描述符指针
DMADPR1，PCI重置0描述符位置后偏移$A4位描述读写值。写入一（1）表示PCI地址空间。写入零（0）表示本地地址空间。0 1链结束。写一（1）表示链结束。写入零（0）表示链描述符的结束。（与块模式相同。）0 2终端计数后中断。写入一（1）导致在到达该描述符之前的终端计数之后断言中断。写一个零禁止中断被断言。0 3传输方向。写入一（1）表示从本地总线到PCI总线的传输。写入零（0）表示从PCI总线到本地总线的传输。0 31:4下一个描述符地址。Q字对齐（位[3:0]=0000）$0表3-56 DMA通道0命令/状态寄存器位图DMA通道1命令/状态：DMACSR0，偏移$A8位描述PCI复位0通道0启用后的读写值。写入一（1）使通道能够传输数据。写入零（0）将禁止通道开始DMA传输，如果正在传输数据，则暂停传输（暂停）。0 1频道0启动。如果通道启用，写入一（1）会导致通道开始传输数据/设置0 2通道0中止。写入一（1）会导致通道中止当前传输。通道0启用位必须清除（位[0]=0）。当中止完成时，设置通道0完成（位[4]=1）/设置0 3通道0清除中断。写入一（1）清除通道0中断/Clr 0 4通道0完成。读取一（1）表示通道传输完成。读取零（0）表示通道传输未完成。1 7:5保留。
DMA Channel 1 Descriptor Pointer
DMADPR1, PCI resets the 0 descriptor position and offsets $A4 bit to describe the read/write value. Write one (1) to indicate the PCI address space. Writing zero (0) indicates the local address space. 0 1 end of chain. Write one (1) to indicate the end of the chain. Writing zero (0) indicates the end of the chain descriptor. (Same as block mode.) 0 2 Interrupt after terminal count. Writing one (1) causes an interrupt to be asserted after the terminal count before reaching the descriptor. Writing a zero forbidden interrupt is asserted. 0 3 transmission direction. Write one (1) indicates the transfer from the local bus to the PCI bus. Writing zero (0) indicates the transfer from the PCI bus to the local bus. 0 31:4 Next descriptor address. Q word alignment (bit [3:0]=0000) $0 Table 3-56 DMA channel 0 command/status register bitmap DMA channel 1 command/status: DMACSR0, offset $A8 bit describes the read/write value after PCI reset 0 channel 0 is enabled. Write one (1) to enable the channel to transmit data. Writing zero (0) will prevent the channel from starting DMA transfer, and if data is being transferred, suspend the transfer (pause). 0 1 Channel 0 started. If the channel is enabled, writing one (1) causes the channel to start transmitting data/setting 0 2 Channel 0 to abort. Writing one (1) causes the channel to abort the current transmission. The channel 0 enable bit must be cleared (bit [0]=0). When the abort is completed, set channel 0 to complete (bit [4]=1)/set 0 3 channel 0 to clear the interrupt. Write one (1) clear channel 0 interrupt/Clr 0 4 channel 0 complete. One (1) read indicates that the channel transmission is completed. Reading zero (0) indicates that the channel transmission is not completed. 1 7:5 Reserved.
DMA通道1命令/状态
DMACSR1，关闭$A8位描述PCI Re 0通道1启用后的读写值。写入一（1）使通道能够传输数据。写入零（0）将禁止通道开始DMA传输，如果正在传输数据，则暂停传输（暂停）。0 1频道1启动。如果通道启用，写入一（1）会导致通道开始传输数据。/0 2通道1中止。写入一（1）会导致通道中止当前传输。通道1启用位必须清除（位[0]=0）。s通道1完成（位[4]=1），中止完成。/0 3通道1清除中断。写入一（1）清除通道1中断/Clr 0 4通道1完成。读取一（1）表示通道传输完成。读取零（0）表示通道传输未完成。1 7:5保留。000表3-58模式/DMA仲裁寄存器位图模式/DMA判优：MARBR、关闭$AC或$12C位描述初始化后读写值7:0本地总线延迟定时器。在解除保持和释放本地总线之前发生的本地总线时钟周期数$0 15:8本地总线暂停计时器。释放本地总线后，在重新启动保持之前发生的本地总线时钟周期数。暂停计时器仅在DMA期间有效$0 16本地总线延迟计时器启用。写一（1）启用暂停计时器。写入零（0）将禁用暂停计时器。0 17本地总线暂停计时器启用。写入一（1）将启用暂停计时器。写入零（0）将禁用暂停计时器。0 18本地总线BREQ启用。写入一（1）启用本地总线BR#/BREQi。当BR#/BREQi激活时，PLX 9656取消保持并释放
DMA channel 1 command/status
DMACSR1, turn off bit $A8 to describe the read/write value after PCI Re 0 channel 1 is enabled. Write one (1) to enable the channel to transmit data. Writing zero (0) will prevent the channel from starting DMA transfer, and if data is being transferred, suspend the transfer (pause). 0 1 Channel 1 started. If the channel is enabled, writing one (1) causes the channel to start transmitting data/ 0 2 Channel 1 aborted. Writing one (1) causes the channel to abort the current transmission. The channel 1 enable bit must be cleared (bit [0]=0). S Channel 1 completed (bit [4]=1), abort completed/ 0 3 Channel 1 clear interrupt. Write one (1) clear channel 1 interrupt/Clr 0 4 channel 1 complete. One (1) read indicates that the channel transmission is completed. Reading zero (0) indicates that the channel transmission is not completed. 1 7:5 Reserved. 000 Table 3-58 Mode/DMA Arbitration Register Bitmap Mode/DMA Judgment: MARBR, Close $AC or $12C Bits Description After Initialization Read/Write Value 7:0 Local Bus Delay Timer. The number of local bus clock cycles that occurred before the local bus was released from hold and release $0 15:8 The local bus pause timer. The number of local bus clock cycles that occur before restart hold after the local bus is released. The suspend timer is only valid during DMA. $0 16 The local bus delay timer is enabled. Write one (1) to enable the pause timer. Writing zero (0) disables the pause timer. 0 17 Local bus pause timer enabled. Writing one (1) will enable the pause timer. Writing zero (0) disables the pause timer. 0 18 Local bus BREQ enabled. Write one (1) to enable local bus BR #/BREQi. When BR #/BREQi is active, PLX 9656 cancels holding and releases
