5751017-A工控备件
配置寄存器
基本目标写入和读取操作几乎不需要或不需要软件。电路板将在功能模式下通电。然而，当板安装在新系统中时，用户必须至少检查一次PCI配置寄存器（基本地址寄存器0、1、2和3），以了解系统BIOS将其他寄存器组和反射存储器放置在何处。寄存器组和反射存储器的位置会因系统而异，甚至可能因系统中的插槽而异。对于超出基本设置的操作，如启用或禁用中断或执行DMA循环，用户必须知道五个寄存器组内寄存器的特定位分配。该信息在本章中提供。这五个寄存器集是：•PCI配置寄存器•本地配置寄存器•运行时寄存器•DMA控制寄存器•RFM控制和状态寄存器PLX 9656 PCI接口设备是一种高度通用的设备，适用于多种操作。因此，这些集合中的许多寄存器以及每个寄存器中的许多位函数不适用于操作。以下部分将努力指出那些明显不适用的寄存器和位函数。然而，为了保持通用性，包含了可能有用途的寄存器。PLX 9656 PCI接口设备能够在三种不同的本地总线模式下工作。三种模式为“M”、“C”和“J”。此外，本地总线可以以8、16或32位的宽度构造。总线模式和宽度影响寄存器和位函数的应用。请注意，PLX 9656设备为硬接线，可在J模式下运行，总线宽度为32位。
Configuration register
Basic target write and read operations require little or no software. The circuit board will power up in functional mode. However, when the board is installed in a new system, the user must check the PCI configuration registers (basic address registers 0, 1, 2, and 3) at least once to understand where the system BIOS places other register groups and reflective memory. The location of register groups and reflective memory varies from system to system, and may even vary from slot to slot in the system. For operations beyond the basic settings, such as enabling or disabling interrupts or executing DMA cycles, the user must know the specific allocation of registers in the five register groups. This information is provided in this chapter. The five register sets are: • PCI configuration register • Local configuration register • Runtime register • DMA control register • RFM control and status register PLX 9656 PCI interface device is a highly versatile device, which is suitable for multiple operations. Therefore, many registers in these sets and many bit functions in each register are not suitable for operations. The following sections will try to point out those registers and bit functions that are obviously not applicable. However, in order to maintain universality, registers that may be useful are included. The PLX 9656 PCI interface device can operate in three different local bus modes. The three modes are "M", "C" and "J". In addition, the local bus can be constructed with a width of 8, 16, or 32 bits. Bus mode and width affect the application of registers and bit functions. Note that the PLX 9656 device is hardwired and can operate in J mode with a bus width of 32 bits.
PCI配置寄存器
PCI配置寄存器位于PCI配置空间的256字节中，遵循PCI规范v2.2定义的模板。PCI配置空间中的前64字节由完全预定义的头组成。在该报头区域内，每个设备只实现必要的和相关的寄存器。然而，报头区域中存在的所有寄存器和位函数必须符合PCI规范的定义。在第一个64字节边界之外，每个设备都可以实现额外的设备唯一寄存器。目前，PLX 9656实现了14个附加寄存器。尽管PCI配置寄存器可以随时访问，但用户很少更改它们。
PCI configuration register
The PCI configuration register is located in 256 bytes of the PCI configuration space and follows the template defined in PCI specification v2.2. The first 64 bytes in the PCI configuration space consist of fully predefined headers. Within this header area, each device implements only the necessary and related registers. However, all registers and bit functions present in the header area must conform to the PCI specification definition. Outside the first 64 byte boundary, each device can implement additional device unique registers. At present, the PLX 9656 implements 14 additional registers. Although PCI configuration registers can be accessed at any time, users rarely change them.
