电平敏感
PCI中断外围组件互连（PCI）本地总线上的中断是可选的，并定义为“电平敏感”，使用漏极开路输出驱动器断言为低（负真）。中断线INTx#的断言和反断言与CLK异步。设备在请求其设备驱动程序注意时断言其INTx#行。一旦INTx#信号被断言，它将保持断言，直到设备驱动程序清除未决请求。当请求被清除时，设备取消断言其INTx#信号。PCI为单个功能设备定义了一条中断线，为多功能设备或连接器定义了多达四条中断线。对于单功能设备，只能使用INTA#，而其他三条中断线没有意义。第47页的图2-1描述了与VME操作和PMC站点相关的中断逻辑。多功能设备上的任何功能都可以连接到任何INTx#线。中断引脚寄存器定义函数用于请求中断的INTx#线。如果一个设备实现了一条INTx#线，它被称为INTA#；如果它实现了两行，它们被称为INTA#和INTB#；等等对于多功能设备，所有功能都可以使用相同的INTx#行，或者每个功能都可以有自己的（最多四个功能），或者它们的任意组合。单个函数永远不能在多个INTx#行上生成中断请求。
PCI设备中断映射
从属PIC通过BIOS定义的线路接受VME中断。BIOS根据哪个系统需要使用中断线来定义要使用的中断线。PCI设备中断映射基于PCI总线的外部设备包括PMC站点、以太网控制器和PCI到VME桥。默认BIOS将这些外部设备映射到ICH2的PCI中断请求（PIRQx）线。该映射如图所示，。无法修改每个设备上存在的设备PCI中断线（INTA到INTD）。
Level sensitive
PCI Interrupt Interrupts Interrupts on the Peripheral Component Interconnect (PCI) local bus are optional and defined as "level sensitive" and asserted as low (negative true) using an open drain output driver. The assertion and anti assertion of interrupt line INTx # are asynchronous with CLK. The device asserts its INTx # line when requesting its device driver attention. Once the INTx # signal is asserted, it will remain asserted until the device driver clears the pending request. When the request is cleared, the device unasserts its INTx # signal. PCI defines one middle break for a single functional device and up to four middle breaks for a multi-function device or connector. For the single function equipment, only INTA # can be used, while the other three medium line breaks are meaningless. Figure 2-1 on page 47 describes the interrupt logic associated with VME operations and PMC sites. Any function on the multi-function device can be connected to any INTx # line. The interrupt pin register defines the INTx # line whose function is used to request interrupts. If a device implements an INTx # line, it is called INTA #; If it implements two lines, they are called INTA # and INTB #; For multi-function devices, all functions can use the same INTx # line, or each function can have its own (up to four functions), or any combination of them. A single function can never generate an interrupt request on multiple INTx # lines.
PCI device interrupt mapping
The slave PIC accepts VME interrupts through the line defined by the BIOS. The BIOS defines the interrupt line to be used according to which system needs to use the interrupt line. PCI device interrupt mapping PCI bus based external devices include PMC sites, Ethernet controllers, and PCI to VME bridges. The default BIOS maps these external devices to the PCI Interrupt Request (PIRQx) line of ICH2. The mapping is shown in the figure,. The device PCI middle line break (INTA to INTD) present on each device cannot be modified.
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