特殊的输入/输出指令
I/O端口映射与桌面系统一样，3BHE022886R0001包括特殊的输入/输出指令，用于访问I/O寻址空间中的I/O外围设备（与内存寻址空间分离且不同）。I/O地址空间中的位置称为端口。当CPU解码并执行I/O指令时，它在线A00至A15上产生一个16位I/O地址，并用M/I/O控制线识别I/O周期。因此，CPU包括一个独立的64KB I/O地址空间，可作为字节、字或长字访问。标准硬件电路仅为外围设备保留1024字节的I/O寻址空间，从I/O$000到$3FF。所有标准的PC I/O外围设备，如串行和并行端口、硬盘和软盘驱动器控制器、视频系统、实时时钟、系统计时器和中断控制器都在I/O空间的这一区域中进行处理。BIOS正确初始化和配置所有这些寄存器；通常不需要直接调整这些I/O端口。分配的和用户可用的I/O地址汇总在I/O地址中
单独的硬件中断线分配
系统中断除了I/O端口地址外，I/O设备还具有单独的硬件中断线分配。分配给每个中断行的是存储器中$00000到$003FF的256矢量中断表中的相应中断矢量。列出了16个可屏蔽中断和单个不可屏蔽中断（NMI）及其功能。详细说明了中断向量表中的向量。也为实模式和保护模式定义了十六进制和十进制的中断数。3BHE022886R0001上的中断硬件实现是基于PC架构（从IBM PC/XT演变而来）构建的计算机的标准。在IBM PC/XT计算机中，只有八条中断请求线存在，在PIC上编号为IRQ0到IRQ7。IBM PC/AT计算机通过将第二个从PIC级联到原始主PIC中，又增加了八条IRQx线，编号为IRQ8到IRQ15。主PIC处的IRQ2被提交作为从PIC的级联输入。
Special input/output instructions
Like desktop systems, 3BHE022886R0001 includes special I/O instructions for accessing I/O peripherals in the I/O addressing space (separate from and different from the memory addressing space). The location in the I/O address space is called a port. When the CPU decodes and executes the I/O instruction, it generates a 16 bit I/O address from A00 to A15, and uses the M/I/O control line to identify the I/O cycle. Therefore, the CPU includes an independent 64KB I/O address space that can be accessed as bytes, words, or long words. The standard hardware circuit only reserves 1024 bytes of I/O addressing space for peripheral devices, from I/O $000 to $3FF. All standard PC I/O peripherals, such as serial and parallel ports, hard disk and floppy disk drive controllers, video systems, real-time clocks, system timers, and interrupt controllers, are processed in this area of the I/O space. BIOS correctly initializes and configures all these registers; These I/O ports usually do not need to be adjusted directly. Allocated and user available I/O addresses are summarized in I/O addresses
Disconnection allocation in separate hardware
In addition to the I/O port address, the I/O device also has separate hardware disconnection allocation. Each interrupt row is assigned the corresponding interrupt vector in the 256 vector interrupt table of $00000 to $003FF in memory. The 16 maskable interrupts and a single non maskable interrupt (NMI) and their functions are listed. The vectors in the interrupt vector table are described in detail. Hexadecimal and decimal interrupt numbers are also defined for real mode and protected mode. The interrupt hardware implementation on 3BHE022886R0001 is a computer standard based on PC architecture (evolved from IBM PC/XT). In the IBM PC/XT computer, only eight interrupt request lines exist, numbered IRQ0 to IRQ7 on the PIC. By cascading the second PIC to the original main PIC, the IBM PC/AT computer adds eight IRQ x-rays, numbered IRQ8 to IRQ15. IRQ2 at the master PIC is submitted as a cascading input to the slave PIC.
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