AMAT 0100-20001系统电子接口 PCB
1.产 品 资 料 介 绍：
中文资料：
AMAT 0100-20001规范没有指定多字节传输的哪个字节最重要。然而，AMAT 0100-20001规范确实要求某些字节通道与某些字节地址相关联。如第31页表1-1所示，在L字传输期间，字节（0）必须在数据线D31-D24上传输，而字节（3）必须在线D7-D0上传输。这种字节和地址对齐与诸如Motorola 68040之类的Big Endian处理器完全相同。
如果Little Endian设备的数据总线直接连接到AMAT 0100-20001（即D31到D31、D30到D30等），那么在L字写入期间提供给AMAT 0100-20001 D31-D24字节通道的最高有效字节数据将由AMAT 0100-20001存储在四个目的地字节地址中的最低地址中——与Pentium微处理器预期的相反。
如果写入的32位值总是使用类似的L字传输（即一次读取所有四个字节）进行读取，则这不会带来问题，因为交换的数据会再次交换，并在主机上完全显示。然而，如果要使用任何其他方法检索由32位L字传输写入的数据，例如，使用四个单独的字节传输会产生问题。最低字节地址的数据会被错误地认为是最低有效的，而实际上它是最高有效的。
英文资料：
The AMAT 0100-20001 Specification does not specify which byte of a multiple-byte transfer is most significant. The AMAT 0100-20001 Specification does, however, require certain byte lanes to be associated with certain byte addresses. As shown in Table 1-1 on page 31, byte(0) must be transferred on data lines D31-D24 during a Lword transfer while byte(3) must be transferred on lines D7-D0. This byte and address alignment is exactly the same as that for a Big Endian processor such as the Motorola 68040.
If a Little Endian device were to have its data bus directly connected to the AMAT 0100-20001 (i.e., D31 to D31, D30 to D30, etc.), then the most significant byte data supplied to the AMAT 0100-20001 D31-D24 byte lane during a Lword write would be stored by the VAMAT 0100-20001in the lowest of the four destination byte addresses – opposite that expected by the Pentium microprocessor.
This poses no problem if the 32-bit value written is always read back using a similar Lword transfer (i.e., all four bytes at once), since the swapped data gets swapped again and appears to the Host exactly as it should. However, if the data written by the 32-bit Lword transfer were to be retrieved using any other method, for example, using four separate byte transfers creates a problem. The data at the lowest byte address would be incorrectly assumed to be the least significant, while it is actually the most significant.
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